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IEEE Standard VHDL Language Reference Manual
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Available format(s): PDF
Superseded date: 23-12-2019
Language(s): English
Published date: 26-01-2009
Publisher: Institute of Electrical & Electronics Engineers
1 Overview of this standard 1.1 Scope 1.2 Purpose 1.3 Structure and terminology of this standard2 Normative references3 Design entities and configurations 3.1 General 3.2 Entity declarations 3.3 Architecture bodies 3.4 Configuration declarations4 Subprograms and packages 4.1 General 4.2 Subprogram declarations 4.3 Subprogram bodies 4.4 Subprogram instantiation declarations 4.5 Subprogram overloading 4.6 Resolution functions 4.7 Package declarations 4.8 Package bodies 4.9 Package instantiation declarations 4.10 Conformance rules5 Types 5.1 General 5.2 Scalar types 5.3 Composite types 5.4 Access types 5.5 File types 5.6 Protected types 5.7 String representations6 Declarations 6.1 General 6.2 Type declarations 6.3 Subtype declarations 6.4 Objects 6.5 Interface declarations 6.6 Alias declarations 6.7 Attribute declarations 6.8 Component declarations 6.9 Group template declarations 6.10 Group declarations 6.11 PSL clock declarations7 Specifications 7.1 General 7.2 Attribute specification 7.3 Configuration specification 7.4 Disconnection specification8 Names 8.1 General 8.2 Simple names 8.3 Selected names 8.4 Indexed names 8.5 Slice names 8.6 Attribute names 8.7 External names9 Expressions 9.1 General 9.2 Operators 9.3 Operands 9.4 Static expressions 9.5 Universal expressions10 Sequential statements 10.1 General 10.2 Wait statement 10.3 Assertion statement 10.4 Report statement 10.5 Signal assignment statement 10.6 Variable assignment statement 10.7 Procedure call statement 10.8 If statement 10.9 Case statement 10.10 Loop statement 10.11 Next statement 10.12 Exit statement 10.13 Return statement 10.14 Null statement11 Concurrent statements 11.1 General 11.2 Block statement 11.3 Process statement 11.4 Concurrent procedure call statements 11.5 Concurrent assertion statements 11.6 Concurrent signal assignment statements 11.7 Component instantiation statements 11.8 Generate statements12 Scope and visibility 12.1 Declarative region 12.2 Scope of declarations 12.3 Visibility 12.4 Use clauses 12.5 The context of overload resolution13 Design units and their analysis 13.1 Design units 13.2 Design libraries 13.3 Context declarations 13.4 Context clauses 13.5 Order of analysis14 Elaboration and execution 14.1 General 14.2 Elaboration of a design hierarchy 14.3 Elaboration of a block, package, or subprogram header 14.4 Elaboration of a declarative part 14.5 Elaboration of a statement part 14.6 Dynamic elaboration 14.7 Execution of a model15 Lexical elements 15.1 General 15.2 Character set 15.3 Lexical elements, separators, and delimiters 15.4 Identifiers 15.5 Abstract literals 15.6 Character literals 15.7 String literals 15.8 Bit string literals 15.9 Comments 15.10 Reserved words 15.11 Tool directives16 Predefined language environment 16.1 General 16.2 Predefined attributes 16.3 Package STANDARD 16.4 Package TEXTIO 16.5 Standard environment package 16.6 Standard mathematical packages 16.7 Standard multivalue logic package 16.8 Standard synthesis packages 16.9 Standard synthesis context declarations 16.10 Fixed-point package 16.11 Floating-point package17 VHDL Procedural Interface overview 17.1 General 17.2 Organization of the interface 17.3 Capability sets 17.4 Handles18 VHPI access functions 18.1 General 18.2 Information access functions 18.3 Property access functions 18.4 Access by name function19 VHPI information model 19.1 General 19.2 Formal notation 19.3 Class inheritance hierarchy 19.4 Name properties 19.5 The stdUninstantiated package 19.6 The stdHierarchy package 19.7 The stdTypes package 19.8 The stdExpr package 19.9 The stdSpec package 19.10 The stdSubprograms package 19.11 The stdStmts package 19.12 The stdConnectivity package 19.13 The stdCallbacks package 19.14 The stdEngine package 19.15 The stdForeign package 19.16 The stdMeta package 19.17 The stdTool package 19.18 Application contexts20 VHPI tool execution 20.1 General 20.2 Registration phase 20.3 Analysis phase 20.4 Elaboration phase 20.5 Initialization phase 20.6 Simulation phase 20.7 Save phase 20.8 Restart phase 20.9 Reset phase 20.10 Termination phase21 VHPI callbacks 21.1 General 21.2 Callback functions 21.3 Callback reasons22 VHPI value access and update 22.1 General 22.2 Value structures and types 22.3 Reading object values 22.4 Formatting values 22.5 Updating object values 22.6 Scheduling transactions on drivers23 VHPI function reference 23.1 General 23.2 vhpi_assert 23.3 vhpi_check_error 23.4 vhpi_compare_handles 23.5 vhpi_control 23.6 vhpi_create 23.7 vhpi_disable_cb 23.8 vhpi_enable_cb 23.9 vhpi_format_value 23.10 vhpi_get 23.11 vhpi_get_cb_info 23.12 vhpi_get_data 23.13 vhpi_get_foreignf_info 23.14 vhpi_get_next_time 23.15 vhpi_get_phys 23.16 vhpi_get_real 23.17 vhpi_get_str 23.18 vhpi_get_time 23.19 vhpi_get_value 23.20 vhpi_handle 23.21 vhpi_handle_by_index 23.22 vhpi_handle_by_name 23.23 vhpi_is_printable 23.24 vhpi_iterator 23.25 vhpi_printf 23.26 vhpi_protected_call 23.27 vhpi_put_data 23.28 vhpi_put_value 23.29 vhpi_register_cb 23.30 vhpi_register_foreignf 23.31 vhpi_release_handle 23.32 vhpi_remove_cb 23.33 vhpi_scan 23.34 vhpi_schedule_transaction 23.35 vhpi_vprintf24 Standard tool directives 24.1 Protect tool directivesAnnex A (informative) Description of accompanying filesAnnex B (normative) VHPI header fileAnnex C (informative) Syntax summaryAnnex D (informative) Potentially nonportable constructsAnnex E (informative) Changes from IEEE Std 1076-2002Annex F (informative) Features under consideration for removalAnnex G (informative) Guide to use of standard packagesAnnex H (informative) Guide to use of protect directivesAnnex I (informative) GlossaryAnnex J (informative) BibliographyIndex
Describes the VHDL language reference manual (LRM) by including a standard C language interface specification; specifications from previously separate, but related, standards IEEE Std 1164[TM]-1993, IEEE Std 1076.2[TM]-1996, and IEEE Std 1076.3[TM]-1997; and general language enhancements in the areas of design and verification of electronic systems.
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