• I.S. EN 60191-6-13:2016

    Current The latest, up-to-date edition.

    MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-13: DESIGN GUIDELINE OF OPEN-TOP-TYPE SOCKETS FOR FINE-PITCH BALL GRID ARRAY (FBGA) AND FINE-PITCH LAND GRID ARRAY (FLGA)

    Available format(s):  Hardcopy, PDF

    Language(s):  English

    Published date:  01-01-2016

    Publisher:  National Standards Authority of Ireland

    For Harmonized Standards, check the EU site to confirm that the Standard is cited in the Official Journal.
    Only cited Standards give presumption of conformance to New Approach Directives/Regulations.

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    Table of Contents - (Show below) - (Hide below)

    National Foreword
    FOREWORD
    INTRODUCTION
    1 Scope
    2 Normative references
    3 Terms and definitions
    4 Socket code
    5 Terminal number
    6 Socket nominal dimension
    7 Socket length and width
    8 Reference symbols and schematics
    9 Individual outline drawing standard registration
    Annex ZA (normative) - Normative references to international
             publications with their corresponding European
             publications

    Abstract - (Show below) - (Hide below)

    Defines a design guideline of open-top-type semiconductor sockets for Fine-pitch Ball Grid Array (FBGA) and Fine-pitch Land Grid Array (FLGA).

    General Product Information - (Show below) - (Hide below)

    Development Note For CENELEC adoptions of IEC publications, please check www.iec.ch to be sure that you have any corrigenda that may apply. (01/2017)
    Document Type Standard
    Publisher National Standards Authority of Ireland
    Status Current

    Standards Referencing This Book - (Show below) - (Hide below)

    IEC 60191-6:2009 Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
    IEC 60191-2:2012 DB Mechanical standardization of semiconductor devices - Part 2: Dimensions
    EN 60191-6:2009 Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
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