Intellectual Property Rights
Foreword
1 Scope
2 References
3 Definitions, symbols and abbreviations
3.1 Definitions
3.2 Symbols
3.3 Abbreviations
4 Primitives associated with layer 1
5 Wiring configurations and location of interface
points
5.1 General
5.2 Support of wiring configurations
6 Functional characteristics
6.1 Interface functions
6.2 Interchange circuits
6.3 Connected/disconnected indication
6.4 Frame structure
6.5 Line code
6.6 Timing considerations
7 Interface procedures
7.1 D-channel access procedure
7.2 Activation/deactivation
7.3 Signals
7.4 Activation/deactivation procedure for TEs
7.5 Activation/deactivation for NTs
7.6 Timer values
7.7 Activation times
7.8 Deactivation times
8 Frame alignment procedures
8.1 Frame alignment procedure in the direction
NT to TE
8.2 Frame alignment in the direction TE to NT
8.3 Multi-framing
8.4 Idle channel code on the B channels
9 Electrical characteristics
9.1 Bit rate
9.2 Jitter and bit-phase relationship between TE
input and output
9.3 NT jitter characteristics
9.4 Termination of the line
9.5 Transmitter output characteristics
9.6 Receiver input characteristics
9.7 Isolation from external voltages
9.8 Interconnecting media characteristics
9.9 Standard ISDN basic access TE cord
10 Power Feeding
10.1 Reference configuration
10.2 Power available from NT
10.3 Power available at a TE
10.4 Power source 1 consumption
10.5 Galvanic isolation
10.6 Current transient
10.7 Current unbalance
10.8 Additional requirements for an APS
10.9 Additional requirements for NT1 restricted
mode source for compatibility with an APS
11 Interface connector contact
Annex A (informative): Wiring configurations and round
trip delay considerations used as a basis for
electrical characteristics
A.1 Introduction
A.2 Wiring configurations
Annex B (normative): Test configurations
Annex C (normative): Test loopbacks defined for the
basic UNI
C.1 Introduction
C.2 Loopback mechanism definitions
C.3 Test loopback reference configuration
C.4 Test loopback characteristics
Annex D (normative): Additional requirements applicable
to the (explicit) S reference point
D.1 Introduction
D.2 References
D.3 Definitions
D.4 Conformance
D.5 Requirements
D.6 Provision of power
Annex E (informative): SDL representation of a possible
implementation of the D-channel Access
Annex F (informative): SDL representation of
activation/deactivation procedures for
TEs and NTs
F.1 SDL representation of activation/deactivation
procedures for TEs
F.2 SDL representation of activation/deactivation
procedures for NTs
Annex G (informative): Multi-framing mechanism
G.1 Multi-framing
G.2 S-channel structuring algorithm
History