IEC TR 63051:2017

Current

Current The latest, up-to-date edition.

Documentation on design automation subjects - Mathematical algorithm hardware description languages for system level modeling and verification (HDLMath)

Available format(s): Hardcopy, PDF, PDF 3 Users, PDF 5 Users, PDF 9 Users

Language(s): English

Published date: 10-01-2017

Publisher: International Electrotechnical Committee

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FOREWORD
INTRODUCTION
1 Scope
2 Normative references
3 Terms and definitions
4 Definition and positioning of HDLMath
5 Functional requirements of HDLMath
6 Comparison of current HDLMath languages
7 Conclusion
Bibliography

Abstract - (Show below) - (Hide below)

IEC TR 63051:2017(E) describes the main functional requirements for an HDLMath language and compares existing HDLMath languages from the viewpoint of designers. It is intended to accelerate the standardization of a mathematical algorithm design language and to help establish a new and good system modeling and verification environment.

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Development Note	Stability Date: 2022. (01/2017)
Document Type	Technical Report
ISBN
Pages
Published
Publisher	International Electrotechnical Committee
Status	Current

International Equivalents – Equivalent Standard(s) & Relationship - (Show below) - (Hide below)

Equivalent Standard(s)	Relationship
PD IEC/TR 63051:2017	Identical

Standards Referencing This Book - (Show below) - (Hide below)

IEC 61691-1-1:2011	Behavioural languages - Part 1-1: VHDL Language Reference Manual
IEC 62530:2011	SystemVerilog - Unified Hardware Design, Specification, and Verification Language
IEC TR 62856:2013	Documentation on design automation subjects - The Bird's-eye View of Design Languages (BVDL)

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