Intellectual Property Rights
Foreword
Introduction
1 Scope
2 References
3 Definitions and abbreviations
3.1 Definitions
3.2 Abbreviations
4 Overview of FSTE
4.1 Mapping structure of FSTE
4.2 FSTE block layer
4.3 TETRA ACELP
5 Block format and procedures for FSTE
5.1 General requirements for FSTE
5.2 FSTE block format
5.3 Block synchronization
5.4 Block error
5.5 Control bits
5.6 Spare bits
6 Overview of OSTE
6.1 Mapping structure of OSTE
6.2 OSTE block layer
6.3 TETRA ACELP
7 Block format and procedures for OSTE
7.1 General requirements
7.2 OSTE block format
7.3 Block synchronization
7.4 Block error
7.5 Control bits
7.6 Frame number bits
7.7 Block end and idle bits
Annex A (informative): Support of circuit mode services
A.1 Background
A.2 Block format and procedures
Annex B (informative): Bibliography
History