Foreword
Introduction
1 Scope
2 Normative References
2.1 Overview
2.2 Approved References
2.3 References under Development
3 Definitions and Conventions
3.1 Overview
3.2 Definitions
3.3 Editorial Conventions
3.4 Abbreviations, acronyms, and symbols
3.5 Keywords
3.6 State Diagram notation
3.6.1 State Diagram conventions
3.6.2 State Diagram variables
3.6.3 State Diagram timers
3.6.4 State transitions
3.6.5 Operators
4 Structure and Concepts
4.1 Overview
4.2 Relationship with other Standards
4.3 FC-BaseT PHY Logical Model
4.4 FC-BaseT usage of XGMII
4.5 Operation of FC-BaseT
4.5.1 Overview
4.5.2 PCS Overview
4.5.3 PMA Overview
4.6 FC-BaseT Service Primitives and Interfaces
4.6.1 Overview
4.6.2 PMA Service Interface
4.6.3 Management Function Interface
4.7 FC-BaseT Nomenclature
5 Physical Coding Sublayer (PCS)
5.1 Overview
5.2 PCS Reset function
5.3 PCS Transmit function
5.3.1 Overview
5.3.2 36/33 Transcoding
5.3.3 Error Detecting Code
5.3.4 PCS Scrambling
5.3.5 Schldfli Lattice Coding
5.3.6 Trellis Coding
5.3.7 Generation of PMA Training Sequences
5.4 PCS Receive Function
5.4.1 Overview
5.4.2 Decoding
5.4.3 PCS Descrambling
5.4.4 33/36 Transcoding
5.4.5 PCS Synchronization
5.5 State Diagrams
6 PMA Sublayer and Medium Dependent Interface
6.1 PMA Overview
6.2 PMA Functions
6.2.1 PMA Reset function
6.2.2 PMA Transmit function
6.2.3 PMA Receive Function
6.2.4 PHY Control Function
6.2.5 Link Monitor Function
6.2.6 Clock Recovery Function
6.2.7 State Diagrams
6.3 PMA Electrical Specification
6.3.1 Isolation and EMC Requirements
6.3.2 Test Modes
6.3.3 Transmitter Electrical Specifications
6.3.4 Receiver Electrical Specifications
6.4 MDI Specification
6.4.1 Overview
6.4.2 MDI Mechanical Specification
6.4.3 Automatic MDI/MDI-X Configuration
6.4.4 MDI Electrical Specification
6.4.5 MDI Fault tolerance
6.5 Link Segment Characteristics
6.5.1 Overview
6.5.2 FC-BaseT Link Topology
6.5.3 FC-BaseT Cable Plant Requirements
7 Elasticity FIFO
7.1 Overview
7.2 Ordered Sets Processing
7.3 Clock Skew Compensation
8 PHY Startup Procedure
8.1 Overview
8.2 Host Speeds Determination
8.3 Host Synchronization
8.4 FC-BaseT Auto-Negotiation
8.4.1 Overview
8.4.2 FC-BaseT Support
8.4.3 Master-Slave Relationship
8.4.4 Cable Length Estimation
8.4.5 Tentative Operating Speed Determination
8.4.6 Configuration Resolution
8.5 Speed Downshift function
8.6 State Diagrams
9 Port Management
9.1 Overview
9.2 FC-BaseT Management Registers
9.3 Control Register
9.4 Status Register
9.5 Speed Downshift Register
9.6 Test Register
9.7 SNR Margin Registers
9.8 Auto-Negotiation Pages Registers
Annexes
Annex A: Additional 36/33 Mappings (Normative)
A.1 Overview
A.2 Notation
A.3 Additional Mappings
Annex B: Schldfli Lattice Coding (Informative)
Annex C: Recommended 4GFC-BaseT Power Schedule
(Informative)
Tables
Figures