ARINC 659 : 1993

1.0 INTRODUCTION
1.1 Purpose of Document
1.2 Document Scope
1.3 Relationship to Other Standards
1.4 ARINC Specification 659 Basic Philosophy
1.5 ARINC Specification 659 Overview
1.6 Support of ARINC Report 651
1.7 Environmental Factors
1.8 Specification Language and Terminology
1.9 Related Documents
2.0 TECHNICAL DESCRIPTION
2.1 Basic Architecture
2.2 Physical Layer
2.3 Data Link Layer
2.4 Data Types
2.5 Table Compatibility
2.6 Error Management
2.7 Test and Maintenance
3.0 PHYSICAL LAYER
3.1 Overview
3.2 Interface Signal Description
3.3 Electrical Performance Characteristics
3.4 Transceiver Enables
3.5 Bus Encoding
3.6 Physical Separation
3.7 Passive Terminator
3.8 LRM Identification
3.9 Connector Pin Assignments
3.10 Power Supply Routing
3.11 Bus Media
4.0 DATA LINK LAYER
4.1 Bus Operation Overview
4.2 Synchronization
4.3 Message Operation
4.4 Receive Data Selection
4.5 Basic Services at BIU/Host Interface
ATTACHMENTS
1 Glossary
2-1 IMA Cabinet Backplane Architecture
2-2 Nomenclature
2-3 Frame Description Language
3-1 Interface Block Diagram
3-2 Interface Signal Names
3-3 Backplane Logic Levels
3-4 Set-Up and Hold Timing
3-5 Data/Clock Skew Measurement Points
3-6 Signal Output Test Circuit
3-7 Bus Encoding Example
3-8 Backplane Terminator Structure
3-9 Insert Pin Assignment for ARINC 650
                Size 1 Connector
3.10 Insert Pin Assignment for ARINC 650
                Size 2 Connector
3-11 Power Supply Routing
4-1 Backplane Activity
4-2 Window Definition Taxonomy
4-3 Initial Frame Definition
4-4 Example Frame Organization
4-5 Window Commands
4-6 BIU State Transition Diagram
4-7 Full-Resolution Time Behavior
4-8 Version Register Components
4-9 Frame Level Synchronization Flow Diagram
4-10 Bit-Level Resync Pulse Timing Example
4-11 Spatial Skew Measurement Points
4-12 Temporal Skew Measurement Points
4-13 XY Skew Measurement Points
4-14 Temporal Resync Inaccuracy Measurement
4-15 XY Resync Inaccuracy Measurement
4-16 Delta (d) Timing Considerations
4-17 Full-Resolution Time Register Components
4-18 Basic Message Structure
4-19 Master/Shadow Message Structure
                (a) Master Transmits
                (b) Shadow 1 Transmits
                (c) Shadow 2 Transmits
                (d) Shadow 3 Transmits
4-20 Initial Sync Message Structure
4-21 Short Resync Message Structure
4-22 Long Resync Message Structure
                (a) Master
                (b) Third Shadow
4-23 Sync Behavior for Long Resync Messages
4-24 Out_of_Sync Behavior for Long Resync Messages
4-25 Data Validation Tables
APPENDICES
A Debug Features

Defines standards for the transfer of digital data between components within an IMA cabinet. Includes the protocol and timing characteristics for a synchronous backplane data bus capable of transferring data at 60 Mbps using a data path that is two bits wide. The electrical characteristics and behavior expected of the participating modules are defined.