BS EN 61691-3-3:2002
Current
The latest, up-to-date edition.
Design automation. Behavioural languages Synthesis in VHDL
Hardcopy
English
08-03-2002
This standard supports the synthesis and verification of hardware designs, by defining vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. Includes package bodies, as described in annex A, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.
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