BS EN 61943:1999

1 General
      1.1 Scope and Object
      1.2 Normative Reference
2 Definitions
3 Principles for Qualified Manufacturer List (QML)
      Approval
      3.1 Identification and definition of tasks
      3.2 Product specifications
4 Process design (Task 1)
      4.1 Field of application
      4.2 Description of activities
      4.3 Interfaces and subcontracting procedures
      4.4 Procedures for design and verification of
             models
      4.5 Procedures for integration and validation
5 Integrated Circuit Design (Task 2)
      5.1 Field of application
      5.2 Description of activities
      5.3 Interfaces
      5.4 Procedures for design and verification
      5.5 Validation procedure
6 Wafer Fabrication (Task 3)
      6.1 Field of application
      6.2 Description of activities
      6.3 Interfaces
      6.4 Validation procedureer or subcontractor
7 Process Characterization (Task 4)
      7.1 Field of application
      7.2 Description of activities
      7.3 Characterization procedures
8 Assembly and Packaging (Task 5)
      8.1 Field of application
      8.2 Description of activities
      8.3 Interfaces
      8.4 Validation procedures
9 Tests (Task 6)
      9.1 Field of application
      9.2 Description of activities
      9.3 Interfaces - Validation of information provided
             by the customer or subcontractor
      9.4 Procedures
      9.5 Validation procedures
Annex ZA (normative) Normative references to international
                     publications with their corresponding
                     European publications

How to apply the principles and requirements given in IEC 61739 to manufacturers of monolithic integrated circuits applying for manufacturing line approval.