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BS IEC 61523-3:2004

Current

Current

The latest, up-to-date edition.

Delay and power calculation standards Standard delay formaty (SDF) for the electronic design process

Available format(s)

Hardcopy , PDF

Language(s)

English

Published date

15-12-2004

€348.24
Excluding VAT

FOREWORD
IEEE Introduction
1 Overview
  1.1 Scope
  1.2 Organization of this standard
2 References
3 Conventions
  3.1 Terminology conventions
  3.2 Syntactic conventions
4 SDF in the design process
  4.1 Sharing of timing data
  4.2 Using multiple SDF files in one design
  4.3 Timing data and constraints
  4.4 Timing environments
  4.5 Back-annotation of timing data for design analysis
  4.6 Forward-annotation of timing constraints for design
      synthesis
  4.7 Timing models supported by SDF
5 Defining the standard delay format
  5.1 SDF file content
  5.2 Header section
  5.3 Cells
  5.4 Delays
  5.5 Timing checks
  5.6 Labels
  5.7 Timing environment
Annex A (normative) Syntax of SDF
Annex B (informative) SDF file examples
Annex C (informative) List of Participants

Describes Standard Delay Format (SDF) an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process. It serve as a complete specification of the Standard Delay Format (SDF). It contains: - Detailed information on how SDF is used in the design process. - Detailed semantic descriptions of all SDF constructs. - The formal syntax. - Examples.

Committee
EPL/501
DocumentType
Standard
Pages
94
PublisherName
British Standards Institution
Status
Current

The Standard Delay Format (SDF)is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process.The ASCII data in the SDF le is represented in a tool and language independent way and includes path delays,timing constraint values,inter-connect delays and high level technology parameters. This standard is published with a double logo IEC-IEEE. standard.

Standards Relationship
IEC 61523-3:2004 Identical

IEEE 1364-2005 IEEE Standard for Verilog Hardware Description Language
IEEE 1076-2008 REDLINE IEEE Standard VHDL Language Reference Manual

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