BS IEC 61523-3:2004
Current
The latest, up-to-date edition.
Delay and power calculation standards Standard delay formaty (SDF) for the electronic design process
Hardcopy , PDF
English
15-12-2004
FOREWORD
IEEE Introduction
1 Overview
1.1 Scope
1.2 Organization of this standard
2 References
3 Conventions
3.1 Terminology conventions
3.2 Syntactic conventions
4 SDF in the design process
4.1 Sharing of timing data
4.2 Using multiple SDF files in one design
4.3 Timing data and constraints
4.4 Timing environments
4.5 Back-annotation of timing data for design analysis
4.6 Forward-annotation of timing constraints for design
synthesis
4.7 Timing models supported by SDF
5 Defining the standard delay format
5.1 SDF file content
5.2 Header section
5.3 Cells
5.4 Delays
5.5 Timing checks
5.6 Labels
5.7 Timing environment
Annex A (normative) Syntax of SDF
Annex B (informative) SDF file examples
Annex C (informative) List of Participants
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