BS IEC 61691-4:2004
Withdrawn
A Withdrawn Standard is one, which is removed from sale, and its unique number can no longer be used. The Standard can be withdrawn and not replaced, or it can be withdrawn and replaced by a Standard with a different number.
Behavioural languages Verilog hardware description language
Hardcopy , PDF
20-04-2012
English
10-11-2004
FOREWORD
IEEE Introduction
1 Overview
2 Lexical conventions
3 Data types
4 Expressions
5 Scheduling semantics
6 Assignments
7 Gate and switch level modeling
8 User-defined primitives (UDPs)
9 Behavioral modeling
10 Tasks and functions
11 Disabling of named blocks and tasks
12 Hierarchical structures
13 Configuring the contents of a design
14 Specify blocks
15 Timing checks
16 Back annotation using the Standard Delay Format (SDF)
17 System tasks and functions
18 Value change dump (VCD) files
19 Compiler directives
20 PLI overview
21 PLI TF and ACC interface mechanism
22 Using ACC routines
23 ACC routine definitions
24 Using TF routines
25 TF routine definitions
26 Using VPI routines
27 VPI routine definitions
Annex A (normative) Formal syntax definition
Annex B (normative) List of keywords
Annex C (informative) System tasks and functions
Annex D (informative) Compiler directives
Annex E (normative) acc_user.h
Annex F (normative) veriuser.h
Annex G (normative) vpi_user.h
Annex H (informative) Bibliography
Annex I (informative) List of Participants
Provides complete specification of the Verilog[R] Hardware Description Language (HDL). It contains: - The formal syntax and semantics of all Verilog HDL constructs; - The formal syntax and semantics of Standard Delay Format (SDF) constructs; - Simulation system tasks and functions, such as text output display commands; - Compiler directives, such as text substitution macros and simulation time scaling; - The Programming Language Interface (PLI) binding mechanism; - The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines; - Informative usage examples; - Informative delay model for SDF; - Listings of header files for PLI.
| Committee |
EPL/501
|
| DevelopmentNote |
Document consists of set of covers (4 pages) and a CD-ROM. (11/2004) Reviewed and confirmed by BSI, January 2008. (12/2007)
|
| DocumentType |
Standard
|
| Pages |
4
|
| PublisherName |
British Standards Institution
|
| Status |
Withdrawn
|
Contains the formal syntax and semantics of all Verilog HDL constructs; the formal syntax and semantics of Standard Delay Format (SDF) constructs; simulation system tasks and functions,such as text output display commands; compiler directives,such as text substitution macros and simulation time scaling; the Programming Language Interface (PLI) binding mechanism; the formal syntax and semantics of access routines,task/function routines,and Verilog procedural interface routines; informative usage examples; informative delay model for SDF; listings of header files for PLI This publication has the status of a double logo IEEE/IEC standard
| Standards | Relationship |
| IEC 61691-4:2004 | Identical |
| IEEE 754-2008 REDLINE | IEEE Standard for Floating-Point Arithmetic |
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