This International Standard provides the semantics definitions for the following categories of information related to electronic circuit designs. Each category of design information is modelled as an EXPRESS schema.
The Core Model consists of 10 schemas. Each of them is presented in this document as a separate chapter. At the beginning of each chapter, a description of the corresponding schema is provided.
The hierarchy_model schema describes the hierarchical information of a cell, i.e. the way a cell may be divided into other cells.
A circuit may be divided into cells which, in turn, may be further subdivided into other cells, thus creating a hierarchy. The hierarchy information describes the cells, the possible cell representations and their instances.
The design_hierarchy_model schema describes the annotation on an occurrence hierarchy.
The definition of a design requires that specific representations (views) of design objects in the hierarchy are selected. This unambiguously creates a configured design hierarchy. This concept is similar to the configuration of a design in VHDL and is related to view selection mechanisms of other electronics design domain information models in industry. The design hierarchy identifies top-level design cells and may provide annotated designspecific data into the elaborated hierarchy.
The connectivity_view_model schema describes the connectivity information of a cell.
This describes the way in which the circuits are connected in order that information or energy may flow from one part of a design or product to another. The Core Model subdivides this information into
the logical_connectivity_model schema which describes the connectivity for a given level of a hierarchy.
Logical connectivity information describes the bit level, abstract electrical connectivity for a given level of a hierarchy, in terms of signals and signal groups.
the connectivity_structure_model schema which describes the structural connectivity of a connectivity view.
Structural connectivity information describes the connectivity, for a given level of a hierarchy, from the structural point of view. The structural connectivity is specified in terms of busses, nets and rippers. Such a structural representation is used to provide support for physical implementation and annotation.
The library_model schema describes the technology information contained in a library, as well as the reusable objects and data.
A library provides a means of grouping cell definitions. A library may be used to group other classes of reusable objects and information as well. Information in a library may be related in terms of technology information.
The information_base_model schema describes the information in an information base.
The information_base describes the kind of information that can be found directly in an information base.
In addition, the following information is also included in the model.
The design_management_model schema provides the design management information.
This information is needed to trace back to the source or the owner of the data.
The documentation_model schema describes the documentation provided for an object.
The support_definition_model schema contains the definition of some auxiliary entities, types and functions that are used by several schemas.
Names of objects used in this Core Model standard were chosen to be the same as the names of the similar objects and concepts in existing electronics domain information models wherever possible.