BS IEC 62142:2005

FOREWORD
IEEE Introduction
1 Overview
  1.1 Scope
  1.2 Compliance to this standard
  1.3 Terminology
  1.4 Conventions
  1.5 Contents of this standard
  1.6 Examples
2 References
3 Definitions
4 Verification methodology
  4.1 Combinational logic verification
  4.2 Sequential logic verification
5 Modeling hardware elements
  5.1 Modeling combinational logic
  5.2 Modeling edge-sensitive sequential logic
  5.3 Modeling level-sensitive storage devices
  5.4 Modeling three-state drivers
  5.5 Support for values x and z
  5.6 Modeling read-only memories (ROM)
  5.7 Modeling random access memories (RAM)
6 Pragmas
  6.1 Synthesis attributes
  6.2 Compiler directives and implicit-synthesis defined
       macros
  6.3 Deprecated features
7 Syntax
  7.1 Lexical conventions
  7.2 Data types
  7.3 Expressions
  7.4 Assignments
  7.5 Gate and switch level modeling
  7.6 User-defined primitives (UDPs)
  7.7 Behavioral modeling
  7.8 Tasks and functions
  7.9 Disabling of named blocks and tasks
  7.10 Hierarchical structures
  7.11 Configuring the contents of a design
  7.12 Specify blocks
  7.13 Timing checks
  7.14 Backannotation using the standard delay format
  7.15 System tasks and functions
  7.16 Value change dump (VCD) files
  7.17 Compiler directives
  7.18 PLI
Annex A (informative) Syntax summary
  A.1 Source text
  A.2 Declarations
  A.3 Primitive instances
  A.4 Module and generated instantiation
  A.5 UDP declaration and instantiation
  A.6 Behavioral statements
  A.7 Specify section
  A.8 Expressions
  A.9 General
Annex B (informative) Functional mismatches
  B.1 Non-deterministic behavior
  B.2 Pragmas
  B.3 Using `ifdef
  B.4 Incomplete sensitivity list
  B.5 Assignment statements mis-ordered
  B.6 Flip-flop with both asynchronous reset and asynchronous
       set
  B.7 Functions
  B.8 Casex
  B.9 Casez
  B.10 Making x assignments
  B.11 Assignments in variable declarations
  B.12 Timing delays
Annex C (informative) List of Participants

Defines a set of modeling rules for writing Verilog[R] HDL descriptions for synthesis.

Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.