BS IEC 62530:2007
Superseded
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
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Standard for SystemVerilog. Unified hardware design, specification and verification language
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
31-12-2007
Publisher
Superseded date
01-01-2011
Superseded by
€365.60
Excluding VAT
| Committee |
EPL/501
|
| DocumentType |
Standard
|
| Pages |
664
|
| PublisherName |
British Standards Institution
|
| Status |
Superseded
|
| SupersededBy |
Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>
| Standards | Relationship |
| IEC 62530:2011 | Identical |
| IEC 62530:2007 | Identical |
| IEC 60950-23:2005 | Identical |
Summarise
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