BS IEC 62530:2021
Current
The latest, up-to-date edition.
SystemVerilog. Unified Hardware Design, Specification, and Verification Language
Hardcopy , PDF
English
19-08-2021
This standard provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.
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