BS IEC 796-1:1990

Foreword
Preface
Introduction
SECTION ONE - GENERAL
1.1 Scope
1.2 Object
1.3 Definitions
1.3.1 General System Terms
1.3.1.1 Compatibility (IEC Publication 625-1)
1.3.1.2 Bus Cycle
1.3.1.3 Interface (IEC Publication 625-1)
1.3.1.4 Interface System (IEC Publication 625-1)
1.3.1.5 Override
1.3.1.6 System
1.3.2 Signals and Paths (IEC Publication 625-1)
1.3.2.1 Bus (IEC Publication 625-1)
1.3.2.2 Byte
1.3.2.3 Word
1.3.2.4 Signal (IEC Publication 625-1)
1.3.2.5 Signal Parameter (IEC Publication 625-1)
1.3.2.6 Signal Level (IEC Publication 625-1)
1.3.2.7 High State (IEC Publication 625-1)
1.3.2.8 Low State (IEC Publication 625-1)
1.3.2.9 Signal Line (IEC Publication 625-1)
1.3.2.10 Master
1.3.2.11 Slave
SECTION TWO - FUNCTIONAL SPECIFICATIONS
2.1 Bus Elements
2.1.1 Masters
2.1.2 Slaves
2.1.3 Bus Signals
2.1.3.1 Control Lines
2.1.3.1.1 Clock Lines
2.1.3.1.2 Command Lines (MWTC*, MRDC*, IOWC*, IORC*)
2.1.3.1.3 Transfer Acknowledge Line (XACK*)
2.1.3.1.4 Initialize (INIT*)
2.1.3.1.5 Lock (LOCK*)
2.1.3.2 Address and Inhibit Lines
2.1.3.2.1 Address Lines (24 lines)
2.1.3.2.2 Byte High Enable Line (BHEN*)
2.1.3.2.3 Inhibit Lines (INH1* and INH2*)
2.1.3.3 Data Lines
2.1.3.4 Interrupt Lines
2.1.3.4.1 Interrupt Request Lines (INT0*-INT7*)
2.1.3.5 Bus Exchange Lines
2.1.3.5.1 Bus Request (BREQ*)
2.1.3.5.2 Bus Priority (BPRN* and BPRO*)
2.1.3.5.4 Common Bus Request (CBRQ*)
2.2 Data Transfer Operation
2.2.1 Data Transfer Overview
2.2.2 Signal Descriptions
2.2.2.1 Initialize (INIT*)
2.2.2.2 Constant Clock (CCLK*)
2.2.2.3 Address Lines (A0*-A23*)
2.2.2.4 Data Lines (D0*-D15*)
2.2.2.5 Bus Commands
2.2.2.5.1 Read Operation
2.2.2.5.2 Write Operation
2.2.2.5.3 Transfer Acknowledge (XACK*)
2.2.2.5.4 Inhibit (INH1* and INH2*)
2.2.2.6 Lock (LOCK*)
2.3 Interrupt Operations
2.3.1 Interrupt Signal Lines
2.3.1.1 Interrupt Request Lines (INT0*-INT7*)
2.3.1.2 Interrupt Acknowledge (INTA*)
2.3.2 Classes of Interrupt Implementation
2.3.2.1 Non-Bus Vectored Interrupts
2.3.2.2 Bus Vectored Interrupts
2.4 Bus Exchange
2.4.1 Bus Exchange Signals
2.4.1.1 Bus Clock (BCLK*)
2.4.1.2 Bus Busy (BUSY*)
2.4.1.3 Bus Priority IN (BPRN*)
2.4.1.4 Bus Priority OUT (BPRO*)
2.4.1.5 Bus Request (BREQ*)
2.4.1.6 Common Bus Request (CBRQ*)(Optional)
2.4.2 Bus Exchange Priority Techniques
2.4.2.1 Serial Priority Technique
2.4.2.2 Parallel Arbitration Technique
SECTION THREE - ELECTRICAL SPECIFICATIONS
3.1 General Bus Considerations
3.1.1 Logical and Electrical State Relationships
3.1.2 Signal Line Characteristics
3.1.2.1 In-Use Signal Line Requirements
3.1.2.2 Backplane Signal Trace Characteristics
3.1.3. Power Supply Specification
3.1.4 Temperature and Humidity
3.2 Timing
3.2.1 Read Operations (I/O and Memory)
3.2.2 Write Operations (I/O and Memory)
3.2.3 Inhibit Operations
3.2.4 Interrupt Implementations
3.2.4.1 NBV Interrupts
3.2.4.2 BV Interrupts
3.2.5 Bus Control Exchanges
3.2.5.1 Serial Priority
3.2.5.2 Parallel Priority
3.2.6 Miscellaneous Timing
3.3 Receivers, Drivers and Terminations
SECTION FOUR - LEVELS OF COMPLIANCE
4.1 Variable Elements of Capability
4.1.1 Data Path
4.1.2 Memory Address Path
4.1.3 I/O Address Path
4.1.4 Interrupt Attributes
4.2 Masters and Slaves
4.3 Compliance Level Notation
4.3.1 Data Path
4.3.2 Memory Address Path
4.3.3 I/O Address Path
4.3.4 Interrupt Attributes
4.3.5 Example
4.3.6 Compliance Marking

Specifies interface system components, for use in interconnecting data processing, data storage, and peripheral control devices in close couple configuration.