CSA ISO/IEC 14165-122 :2006

FOREWORD
INTRODUCTION
1 Scope
2 Normative references
3 Definitions and conventions
4 Structure and concepts
5 Address
6 FC-AL Ordered Sets
7 FC-AL Primitive Signals and Sequences
8 L_Port operation
9 L_Port state transition tables
10 Loop Initialization procedure
Annex A (normative) - L_Port Elasticity buffer management
Annex B (informative) - Loop Port State Machine examples
Annex C (informative) - Dynamic Half-Duplex
Annex D (informative) - Access unfairness
Annex E (informative) - Half-duplex operation
Annex F (informative) - BB_Credit and Available_BB_Credit
        management example
Annex G (informative) - L_Port clock design options
Annex H (informative) - Mark Synchronization examples
Annex I (informative)- Port Bypass Circuit example and usage
Annex J (informative) - Public L_Ports and Private NL_Ports
        on a Loop
Annex K (informative) - Assigned Loop Identifier
Annex L (informative) - Selective replicate for parallel
        query acceleration
Annex M (informative) - Controlled FC-AL configurations
Annex N (informative) - Insertion modes of Hubs
Annex O (informative) - L_Port power-on considerations
Annex P (informative) - L_Port initialization flow diagram
Annex Q (informative) - Examples of Switch Port Initialization

Specifies signaling interface enhancements for FC-PH, to allow L_Ports to operate with an Arbitrated Loop topology.