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DEFSTAN 21-24(PT1)/2(2000) : 2000

Current

Current

The latest, up-to-date edition.

DATA TRANSMISSION - DIRECT MEMORY ACCESS INTERFACE STANDARD - PART 1: THE SOFTWARE INTERFACE

Available format(s)

Hardcopy , PDF

Language(s)

English

Published date

15-09-2000

Free

TITLE PAGE
SCOPE
Introduction
Software Interface (NES 1024 Part 1)
Electrical Interface (NES 1024 Part 2)
Compatibility with NES 1024 Parts 3 and 4
Compatibility in the absence of an Electrical Interface
FOREWORD
Sponsorship
Conditions of Release
Categories of NES
Related Documents
Health and Safety
Additional Information
CONTENTS
SECTION 1 - PERFORMANCE SPECIFICATION
            1.1 Introduction to the Software Interface
                1.1.1 Principles of Operation
                1.1.2 Message Forms
                1.1.3 Message Routing and Filtering
                1.1.4 Time Synchronization
                1.1.5 Stimulation
                1.1.6 Adaptation
                1.1.7 Testing
                1.1.8 Summary
                1.1.9 Principles of Implementation
            1.2 Scope of the Software Interface Specification
            1.3 Shared Data Area Specifications
                1.3.1 Control and Status (C & S) Table
                1.3.2 C & S Table: Interface Control
                1.3.3 C & S Table: Location of Tables
                1.3.4 C & S Table: Short Message Input
                       Control
                1.3.5 C & S Table: Short Message Output
                       Control
                1.3.6 C & S Table: Communications Status
                1.3.7 C & S Table: Long Message Input Control
                1.3.8 C & S Table: Long Message Output Control
                1.3.9 C & S Table: Time Synchronization
                1.3.10 Input Table and Output Table
                1.3.11 Fields in Input and Output Buffers
                1.3.12 The Message Type Table
                1.3.13 Terminal Unit Data Area
                1.3.14 Summary Figures
                1.3.15 Data Organization
            1.4 Protocol Specification - Initialization and
                Mode Change
                1.4.1 Introduction to Initialization
                1.4.2 The Initialization Protocol
                1.4.3 Host Computer Initialization
                1.4.4 Terminal Unit Initialization
                1.4.5 Introduction to Mode Change
                1.4.6 The Mode Change Protocol (Reset)
                1.4.7 The Mode Change Protocol (Re-initialize)
            1.5 Protocol Specification - Stimulation
                1.5.1 Introduction
                1.5.2 Interrupt Mechanism
                1.5.3 Scanning Mechanism
                1.5.4 Adaptation
                1.5.5 Significant Events
                1.5.6 Stimulation Protocol
                1.5.7 Protocol Examples
            1.6 Protocol Specification - Operation
                1.6.1 Short Message Transmission
                1.6.2 Short Message Output - Action by the Host
                       Computer
                1.6.3 Short Message Output - Action by the
                       Terminal Unit
                1.6.4 Short Message Reception
                1.6.5 Short Message Input - Action by the Terminal
                       Unit
                1.6.6 Short Message Input - Action by the Host
                       Computer
                1.6.7 Long Message Transmission and Reception
                1.6.8 Long Message Output - Action by the Host
                       Computer
                1.6.9 Long Message Output - Action by the
                       Terminal Unit
                1.6.10 Long Message Input - Action by the Host
                       Computer
                1.6.11 Long Message Input - Action by the
                       Terminal Unit
                1.6.12 Number of Short Message Buffers
            1.7 Protocol Specification - Interface Operation
                1.7.1 Time Message Reception
                1.7.2 Time Message Input - Action by Host Computer
                1.7.3 Time Message Input - Action by the Terminal
                      Unit
                1.7.4 Fault Reporting
                1.7.5 Fault Reporting - Action by the Host Computer
                1.7.6 Fault Reporting - Action by the Terminal Unit
SECTION 2 - NATIONAL/INTERNATIONAL REGULATIONS
SECTION 3 - MILITARY STANDARDS/REQUIREMENTS
SECTION 4 - DESIGN REQUIREMENTS/GUIDANCE
SECTION 5 - CORPORATE EXPERIENCE & KNOWLEDGE
ANNEX A - RELATED DOCUMENTS
ANNEX B - DEFINITIONS
ANNEX C - PROCUREMENT CHECK LIST ALPHABETICAL INDEX

Contains the technical requirements for interfacing to current warship combat systems using the CSH or TWSH.

DevelopmentNote
Supersedes DEFSTAN 21-24(PT1)/1(2000) (08/2001) Supersedes NES 1024 PT 1 (08/2003)
DocumentType
Standard
Pages
102
PublisherName
UK Ministry of Defence Standards
Status
Current
Supersedes

DEFSTAN 21-24(PT5)/1(2007) : 2007 DATA TRANSMISSION - INTERFACE STANDARD - PART 5: THE ETHERNET INTERFACE
DEFSTAN 08-107/3(2013) : 2013 GENERAL REQUIREMENTS FOR THE DESIGN OF ELECTROTECHNICAL AND NAVAL WEAPON EQUIPMENT
DEFSTAN 21-59/2(2006) : 2006 SYSTEMS ENGINEERING GUIDE FOR NAVAL COMBAT SYSTEMS
DEFSTAN 21-88/2(2006) : 2006 POLICIES AND PROCEDURES FOR COMBAT SYSTEM INTEGRATION IN SURFACE SHIPS (SSP 88)
DEFSTAN 21-88/1(2003) : 2003 AMD 1 2004 POLICIES AND PROCEDURES FOR COMBAT SYSTEM INTEGRATION IN SURFACE SHIPS (SSP 88)
DEFSTAN 21-24(PT5)/2(2008) : 2008 DATA TRANSMISSION INTERFACE STANDARD - PART 5: THE ETHERNET INTERFACE
DEFSTAN 21-24(PT6)/1(2008) : 2008 DATA TRANSMISSION - INTERFACE STANDARD - PART 6: AN APPLICATION PROGRAM INTERFACE (API) TO THE ETHERNET INTERFACE
DEFSTAN 21-88(PT2)/4(2012) : 2012 POLICIES AND PROCEDURES FOR SYSTEM INTEGRATION IN SURFACE SHIPS - PART 2: THE COMBAT SYSTEM HIGHWAY (CSH)

NES 1024 PT3 : ISSUE 1 DATA TRANSMISSION - DIRECT MEMORY ACCESS INTERFACE STANDARDS - THE ENHANCED SOFTWARE INTERFACE
NES 1024 PT 2 : ISSUE 3 DATA TRANSMISSION - DIRECT MEMORY ACCESS INTERFACE STANDARD - THE ELECTRICAL INTERFACE
BS 5905:1980 Specification for computer programming language CORAL 66
ISO 7498-2:1989 Information processing systems Open Systems Interconnection Basic Reference Model Part 2: Security Architecture
NES 1024 PT4 : ISSUE 1 DATA TRANSMISSION - DIRECT MEMORY ACCESS INTERFACE STANDARDS - THE ENHANCED ELECTRICAL INTERFACE

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