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DEFSTAN 21-24(PT2)/2(2000) : 2000

Current

Current

The latest, up-to-date edition.

DATA TRANSMISSION - DIRECT MEMORY ACCESS INTERFACE STANDARD - PART 2: THE ELECTRICAL INTERFACE

Available format(s)

Hardcopy , PDF

Language(s)

English

Published date

15-09-2000

Free

TITLE PAGE
SCOPE
Introduction
Software Interface (NES 1024 Part 1)
Electrical Interface (NES 1024 Part 2)
Compatibility with NES 1024 Parts 3 & 4
FOREWORD
Sponsorship
Conditions of Release
Categories of NES
Related Documents
Health and Safety
Additional Information
CONTENTS
SECTION 1 - PERFORMANCE SPECIFICATION
            1.1 Introduction to the Electrical Interface
                1.1.1 General
                1.1.2 Real Time Requirements
                1.1.3 Adaptation to Host Word Size
                1.1.4 Reset and Enable Interface Signals
                1.1.5 Mechanical Specifications
            1.2 Facilities Provided by the Interface
                1.2.1 General
                1.2.2 Interface Circuits
                1.2.3 Summary of Facilities Controlled by the
                      Communications Unit
                1.2.4 Summary of Facilities Controlled by the
                      Host Adapter Unit
            1.3 Formal Protocol Rules
                1.3.1 General
                      1.3.1.1 Rule 1
                      1.3.1.2 Rule 2
                      1.3.1.3 Rule 3
                      1.3.1.4 Rule 4
                      1.3.1.5 Rule 5
                      1.3.1.6 Rule 6
                      1.3.1.7 Rule 7
                      1.3.1.8 Rule 8
                      1.3.1.9 Rule 9
                      1.3.1.10 Rule 10
                      1.3.1.11 Rule 11
                      1.3.1.12 Rule 12
                      1.3.1.13 Rule 13
                      1.3.1.14 Rule 14
                      1.3.1.15 Rule 15
                      1.3.1.16 Rule 16
                      1.3.1.17 Rule 17
            1.4 Examples of the Protocol at Work
                1.4.1 General
                1.4.2 Write Data
                1.4.3 Read Data
                1.4.4 Read C&ST Base Address
                1.4.5 Interrupt
            1.5 Electrical and Timing Specifications
                1.5.1 Electrical Specification
                1.5.2 Timing Specifications
SECTION 2 - NATIONAL/INTERNATIONAL REGULATIONS
SECTION 3 - MILITARY STANDARDS/REQUIREMENTS
SECTION 4 - DESIGN REQUIREMENTS/GUIDANCE
SECTION 5 - CORPORATE EXPERIENCE & KNOWLEDGE
ANNEX A - RELATED DOCUMENTS
ANNEX B - DEFINITIONS
ANNEX C - PROCUREMENT CHECK LIST
ANNEX D - GUIDANCE ON WORD LENGTH ADAPTATION
ANNEX E - MECHANICAL REQUIREMENTS FOR EURO CARD
          IMPLEMENTATIONS
ANNEX F
ANNEX G - PETRI NET MODEL OF FORMAL PROTOCOL RULES
ALPHABETICAL INDEX

Contains the technical requirements for interfacing to current warship combat systems using the CSH or TWSH.

DevelopmentNote
Supersedes DEFSTAN 21-24(PT2)/1(2000) (08/2001) Supersedes NES 1024 PT 2 (08/2003)
DocumentType
Standard
Pages
78
PublisherName
UK Ministry of Defence Standards
Status
Current
Supersedes

DEFSTAN 21-24(PT5)/1(2007) : 2007 DATA TRANSMISSION - INTERFACE STANDARD - PART 5: THE ETHERNET INTERFACE
DEFSTAN 08-107/3(2013) : 2013 GENERAL REQUIREMENTS FOR THE DESIGN OF ELECTROTECHNICAL AND NAVAL WEAPON EQUIPMENT
DEFSTAN 21-59/2(2006) : 2006 SYSTEMS ENGINEERING GUIDE FOR NAVAL COMBAT SYSTEMS
DEFSTAN 21-88/2(2006) : 2006 POLICIES AND PROCEDURES FOR COMBAT SYSTEM INTEGRATION IN SURFACE SHIPS (SSP 88)
DEFSTAN 21-88/1(2003) : 2003 AMD 1 2004 POLICIES AND PROCEDURES FOR COMBAT SYSTEM INTEGRATION IN SURFACE SHIPS (SSP 88)
DEFSTAN 21-24(PT5)/2(2008) : 2008 DATA TRANSMISSION INTERFACE STANDARD - PART 5: THE ETHERNET INTERFACE
DEFSTAN 21-24(PT6)/1(2008) : 2008 DATA TRANSMISSION - INTERFACE STANDARD - PART 6: AN APPLICATION PROGRAM INTERFACE (API) TO THE ETHERNET INTERFACE
DEFSTAN 21-88(PT2)/4(2012) : 2012 POLICIES AND PROCEDURES FOR SYSTEM INTEGRATION IN SURFACE SHIPS - PART 2: THE COMBAT SYSTEM HIGHWAY (CSH)

NES 1024 PT3 : ISSUE 1 DATA TRANSMISSION - DIRECT MEMORY ACCESS INTERFACE STANDARDS - THE ENHANCED SOFTWARE INTERFACE
NES 1024 PT 1 : ISSUE 3 DATA TRANSMISSION - DIRECT MEMORY ACCESS INTERFACE STANDARD - THE SOFTWARE INTERFACE
ISO 7498-2:1989 Information processing systems Open Systems Interconnection Basic Reference Model Part 2: Security Architecture
NES 1024 PT4 : ISSUE 1 DATA TRANSMISSION - DIRECT MEMORY ACCESS INTERFACE STANDARDS - THE ENHANCED ELECTRICAL INTERFACE
BS 6475:1984 Specification for processor system bus interface (Eurobus A)

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