DIN IEC 60822:1992-02
Current
The latest, up-to-date edition.
IEC 822 VSB; PARALLEL SUB-SYSTEM BUS OF THE IEC 821 VMEBUS
Hardcopy , PDF
German
01-01-1992
FOREWORD
PREFACE
CHAPTER 0: SCOPE
CHAPTER 1: INTRODUCTION TO THE IEC 822
VSB BUS STANDARD
Section
1.1 Standard objectives of the IEC 822 VSB parallel
Subsystem Bus of the IEC 821 VMEbus (Subsystem
henceforth referred to as VSB)
1.2 VSB System elements
1.2.1 Basic definitions
1.3 VSB Standard diagrams
1.4 Standard terminology
1.4.1 Signal line states
1.4.2 Use of the asterisk (*)
1.5 Protocol specification
CHAPTER 2: VSB DATA TRANSFER BUS
2.1 Introduction
2.2 Data Transfer Bus lines
2.2.1 Addressing lines
2.2.2 Data lines AD00-AD31
2.2.3 Control lines
2.3 DTB modules - Basic description
2.3.1 MASTER
2.3.2 SLAVE
2.4 Capabilities of MASTERS and SLAVES
2.4.1 Addressing capabilities
2.4.2 Data transfer capabilities
2.4.3 Interrupt capability
2.5 Interaction between MASTERS and SLAVES
2.5.1 Interaction between MASTERS and SLAVES
during address broadcast Phase
2.5.2 Interaction between MASTERS and SLAVES
during the data transfer
2.5.3 Interaction between MASTERS and SLAVES
during cycle termination
2.5.4 Interaction between the IHV MASTER and
SLAVES during the INTERRUPT-ACKNOWLEDGE
cycles
2.6 Data transfer bus timing specifications
CHAPTER 3: VSB DATA TRANSFER BUS
ARBITRATION
3.1 Introduction
3.1.1 Types of Arbitration
3.2 Arbitration Bus lines
3.2.1 BREQ*
3.2.2 BUSY*
3.2.3 BGIN*/BGOUT*
3.3 Arbitration modules - Basic description
3.3.1 ARBITER
3.3.2 REQUESTER
3.4 Capabilities of the REQUESTER
3.4.1 Serial Arbitration
3.4.2 Parallel Arbitration capability
3.4.3 Power-up sequence
3.5 Interaction between the MASTER, its associated
REQUESTER and/or its associated ARBITER
3.5.1 Acquisition of the DTB
3.5.2 Release of the DTB
3.5.3 Race conditions between MASTER requests and
ARBITER grants
3.6 Arbitration bus timing specifications
CHAPTER 4: ELECTRICAL CHARACTERISTICS
OF VSB BOARDS
4.1 Introduction
4.1.1 Terminology
4.2 Power distribution
4.2.1 D.C. voltage characteristics
4.2.2 Connector electrical ratings
4.3 Bus driving and receiving requirements
4.3.1 General
4.3.2 Driving and loading RULES for three-state
lines (AD00-AD31, DS*, PAS*, LOCK*,
SIZE0-SIZE1, SPACE0-SPACEl, WR*)
4.3.3 Driving and loading RULES for open-collector
lines (AC, ACK*, AD24-AD31, ASACK0*-
ASACK1*, BREQ*, BUSY*, CACHE*,
ERR*, IRQ*, WAIT*)
4.3.4 Driving and loading RULES for BGIN* and
BGOUT*
4.3.5 Receiving RULES for the geographical
addressing lines (GA0-GA2)
4.3.6 Additional information
4.4 Signal lines interconnection - Summary
CHAPTER 5: VSB BACKPLANE SPECIFICATIONS
5.1 introduction
5.2 Backplane physical characteristics
5.3 Power distribution
5.4 Backplane electrical characteristics
5.4.1 Characteristic impedance
5.4.2 Termination networks
5.5 Signal line interconnection
5.5.1 General
5.5.2 BGIN*/BGOUT* daisy-chain
5.5.3 Geographical addressing
5.5.4 Additional information
5.6 VSB pin assignment
APPENDIX A
Figure
1-1 Functional modules and sub-buses defined by the
VSB standard
1-2 Signal timing notation
2-1 Data Transfer Bus functional block diagram
2-2 Block diagram: MASTER
2-3 Block diagram: SLAVE
2-4 General flow of a VSB cycle
2-5 General flow of an ADDRESS-ONLY cycle
2-6 Organization of data
2-7 General flow of a SINGLE-TRANSFER cycle
2-8 General flow of a BLOCK-TRANSFER cycle
2-9 General flow of an INTERRUPT-ACKNOWLEDGE cycle
2-10 Flow of the address broadcast Phase
2-11 Flow of a write data transfer
2-12 Flow of a read data transfer
2-13 Flow of the termination of the cycle
2-14 Flow of an INTERRUPT-ACKNOWLEDGE cycle
2-15 Active MASTER, active IHV MASTER and active PAR
REQUESTER,
LOCK*, WR*, SIZE0-SIZE1 and SPACE0-SPACE1
timing,
SINGLE-TRANSFER,
BLOCK-TRANSFER,
INTERRUPT-ACKNOWLEDGE and
ARBITRATION cycles
2-16 Active MASTER and SLAVES,
address broadcast timing,
ADDRESS-ONLY,
SINGLE-TRANSFER and
BLOCK-TRANSFER cycles
2-17 Active MASTER and SLAVES, cycle termination
ADDRESS-ONLY cycles
2-18 Active MASTER and SLAVES,
write data transfer timing,
SINGLE-TRANSFER and
BLOCK-TRANSFER cycles
2-19 Active MASTER and SLAVES,
read data transfer timing,
SINGLE-TRANSFER,
BLOCK-TRANSFER and
INTERRUPT-ACKNOWLEDGE cycles
2-20 IHV MASTER and INTV SLAVES, selection
Phase INTERRUPT-ACKNOWLEDGE cycles
2-21 MASTERS and SLAVES intercycle timing
2-22 DTB control transfer timing
2-23 Skew between ASACK0* and ASACK1*
2-24 Skew between ACK* and ERR*
3-1 Arbitration bus functional block diagram
3-2 Block diagram: ARBITER
3-3 Block diagram: SER REQUESTER
3-4 Block diagram: PAR REQUESTER
3-5 Serial Arbitration flow diagram: two
REQUESTERS
3-6 General flow of an ARBITRATION cycle
3-7 Flow of an ARBITRATION cycle
3-8 Flow of the Power-up sequence
3-9 Active PAR REQUESTER, contending PAR
REQUESTER and idle SLAVE ARBITRATION cycle
3-10 Power-up timing
4-1 VSB Signal levels
5-1 VSB backplane dimensions
5-2 Cross-section of a backplane microstrip signal line
5-3 Z[o] versus line width
5-4 C[o] versus line width
5-5 Standard bus termination
5-6 BGIN*/BGOUT* daisy-chain illustration
5-7 Geographical addressing lines resistor/capacitor
circuit
A1 Flow of the selection Phase
A2 Selection Phase control: a high level block diagram
A3 An example for the selection logic
Table
2-1 RULES and PERMISSIONS that specify the use of
the dotted lines by the various types of MASTERS
2-2 RULES and PERMISSIONS that specify the use of
the dotted lines by the various types of SLAVES
2-3 Mnemonics that specify addressing capabilities
2-4 Mnemonic that specifies ADDRESS-ONLY
capability
2-5 Mnemonics that specify the basic data transfer
capabilities of SLAVES
2-6 Mnemonic that specifies BLOCK-TRANSFER
capability
2-7 Mnemonics that specify interrupt capabilities
2-8 Mnemonics that specify STATUS/ID transfer
capabilities of INV MASTERS and INTV SLAVES
2-9 Use of SPACE0 and SPACE1 to select the address
space
2-10 Encoding of SIZE0 and SIZE1 for requested size
of the transfer
2-11 Use of AD00 and AD01 to select the lowest
addressed byte location to be accessed
2-12 Encoding of SIZEO, SIZE1, AD00 and AD01 to
define the byte locations to be accessed
2-13 Encoding of ASACK0* and ASACK1* to define
the size of the SLAVE
2-14 Placement of valid data an AD00-AD31 by the
active MASTER during write cycles
2-15 Use of ADOO-AD31 by a D32 SLAVE to access
byte locations
2-16 Use of AD16-AD31 by a D16 SLAVE to access
byte locations
2-17 Use of AD24-AD31 by a D08 SLAVE to access
byte locations
2-18 Use of SPACE0, SPACE1 and WR* to select an
INTERRUPT-ACKNOWLEDGE cycle
2-19 Use of the data lines by D08, D16 and D32 INTV
SLAVES during INTERRUPT-ACKNOWLEDGE cycles
2-20 Active MASTER, responding SLAVE,
participating SLAVE and idle SLAVE timing
Parameters
2-21 IHV MASTER, responding INTV SLAVE,
contending INTV SLAVE and idle SLAVE timing
Parameters
2-22 MASTER, timing specifications
2-23 SLAVE, timing specifications
3-4 Active PAR REQUESTER, contending PAR
REQUESTER and idle SLAVE timing parameters
3-5 Power-up timing parameters
3-6 Active REQUESTER timing specifications
3-7 Contending REQUESTER timing specifications
3-8 Power-up timing specifications
4-1 Bus driving and receiving requirements
4-2 Signal line interconnection - Summary
5-1 Bus voltage specification
5-2 Signal line termination
5-3 Geographical addressing slot assignment
5-4 VSB pin assignment
Diese Norm definiert einen parallelen Untersystembus (abgekürzt: VSB) als Erweiterung für den IEC 821 VMEbus. Die entsprechende Norm IEC 821 wird derzeit von JTC 1/SC 26 überarbeitet, der zugehörige Internationale Norm-Entwurf ist national als Entwurf DIN IEC 821/09.91, in englischer Sprache veröffentlicht. Der VSB kann bei Bedarf mehrfach in einem VMEbusSystem vorkommen. Er enthält einen asynchronen Hochgeschwindigkeits-Datentransferbus (DTB), der den Mastermodulen die Abwicklung des Datentransfers zu den und von den Slavemodulen erlaubt. Wenn ein Master einen Datenaustausch mit einem oder mehreren Slaves benötigt, löst er entsprechende Buszyklen aus. Der Slave überwacht diese Buszyklen und führt den Datentransfer durch, sofern der Zyklus für ihn bestimmt war. An einem Buszyklus können beliebig viele Slaves beteiligt sein. Die ausgewählten werden iselected Slaves" genannt. Jedoch kann nur ein "responding Slave" genannter Slave antworten, die übrigen ausgewählten Slaves sind "participating Slaves". Nicht ausgewählte Slaves heissen "idle Slaves". Es sind vier Zyklusarten definiert: Address-Only-Zyklus, Einfach-Transfer-Zyklus, Block-Transfer-Zyklus und Interrupt-Acknowledge-Zyklus. Um in Multiprozessor-Systemen die Datentransferraten zu maximieren, definiert diese Norm einen Mechanismus, mit dem der Master die Daten innerhalb eines Zyklusses an eine beliebige Zahl von Slaves gleichzeitig senden kann. Weiterhin unterstützt dieser Mechanismus das sogenannte "DynamicBus-Sizing", "Resource-Locking" und "Data-Caching". Die VSB-Norm definiert darüber hinaus einen Zuteilungsbus, der den Arbiter- und/oder Requester-Modulen die Koordinierung der DTB-Benutzung erlaubt. Es werden zwei Zuteilungsverfahren beschrieben - ein serielles und ein paralleles (verteiltes) Zuteilungsverfahren. Diese Verfahren stellen Protokolle zur Verfügung, mit denen unterschiedliche Untersystem-Architekturen realisiert werden können. Wird ein Untersystem mit einem Master benötigt, welches den Zugriff auf grosse Speicherbereiche erfordert, kann die serielle Zuteilung verwendet werden. Mit diesem Verfahren lässt sich auch ein System mit einem primären Master entwickeln, der die Nutzung des DTB durch weitere, sekundäre Master zulässt, wenn er selbst den DTB nicht benötigt. Schliesslich kann mit dem parallelen Zuteilungsverfahren ein Untersystem für Multiprocessing-Anwendungen realisiert werden.
DocumentType |
Standard
|
Pages |
164
|
PublisherName |
German Institute for Standardisation (Deutsches Institut für Normung)
|
Status |
Current
|
Standards | Relationship |
HD 576 : 200S1 | Corresponds |
IEC 60822:1988 | Identical |
HD 576 : 200S1 | Identical |
DIN 41612-1:1988-01 | TWO-PART CONNECTORS FOR PRINTED BOARD, GRID 2,54 MM; COMMON MOUNTING FEATURES, SURVEY OF TYPES |
DIN 41612-8 Beiblatt 1:1987-10 | TWO-PART CONNECTORS FOR PRINTED BOARDS, GRID 2,54 MM; DIMENSIONS OF TYPE M; SURVEY OF SPECIAL CONTACTS FOR USE WITH TYPE M |
DIN 41612-9:1987-10 | TWO-PART CONNECTORS FOR PRINTED BOARDS; GRIP 2,54 MM; DIMENSIONS OF TYPE E |
DIN 41612-1 Beiblatt 1:1980-05 | TWO PIECE CONNECTORS FOR PRINTED CIRCUITS, GRID 2,54 MM (0,1 IN); GENERAL ALLUSIONS |
DIN 41612-5:1987-10 | TWO-PART CONNECTORS FOR PRINTED BOARDS; GRID 2,54 MM; RATINGS, REQUIREMENTS, TESTS |
DIN 41612-6:1990-06 | TWO-PART CONNECTORS FOR PRINTED BOARD; GRID 2,54 MM; DIMENSIONS OF TYPES Q, R AND S |
DIN 41612-10:1987-10 | TWO-PART CONNECTORS FOR PRINTED BOARDS; GRID 2,54 MM; GAUGES |
DIN 41612-8:1987-10 | TWO-PART CONNECTORS FOR PRINTED BOARDS, GRID 2,54 MM; DIMENSIONS OF TYPE M |
DIN 41612-7:1985-06 | TWO-PART CONNECTORS FOR PRINTED BOARD, GRID 2,54 MM; DIMENSIONS OF TYPES U AND V |
DIN 41612-3:1987-10 | TWO-PART CONNECTORS FOR PRINTED BOARDS; GRID 2,54 MM; DIMENSIONS OF TYPES F AND G |
DIN 41612-2:1987-10 | TWO-PART CONNECTORS FOR PRINTED BOARDS; GRID 2,54 MM; DIMENSIONS OF TYPES B, C AND D |
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