DSCC 15212C:2025
Current
Current
The latest, up-to-date edition.
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2M x 32-BIT (64M), RADIATION-HARDENED, PIPELINED, SYNCHRONOUS SRAM (SSRAM), MONOLITHIC SILICON
Published date
25-07-2025
Publisher
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This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V).
| DocumentType |
Standard
|
| PublisherName |
Defense Supply Centre Columbus
|
| Status |
Current
|
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| MIL-STD-883 Revision L:2019 | Microcircuits |
| JEDEC JESD 65B : 2003 | Definition of Skew Specifications for Standard Logic Devices |
| JEDEC JESD 78E:2016 | IC LATCH-UP TEST |
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