I.S. EN 190116:1993

Cooperating organizations
National foreword
Foreword
Specification
1 Limiting conditions of use for the family
2 Recommended operating and associated characteristics
    for the family
3 Test methods and procedures - mechanical data
4 Inspection requirements
Tables
1 AC series
2 ACT series
3 Untitled
4 Untitled
5 Untitled
Figures
1 Loading circuit
2 Transition times and propagation delay times
3 Clock-pulse rise and fall times and pulse width
4 Set-up times, hold times, removal time and
    propagation delay times for edge triggered
    sequential logic circuits
5 Loading circuits
6 3-state propagation delay wave shapes
7 Loading circuit
8 Transition times and propagation delay times
9 Clock-pulse rise and fall times and pulse width
10 Set-up times, hold times, removal time and
    propagation delay tunes for edge triggered
    sequential logic circuits
11 Loading circuit
12 3-state propagation delay wave shapes
13 Untitled
14 Input pulse waveforms
15 Example of test set-up for positive and negative
    trigger current
16 Timing for latch-up immunity tests
17 Untitled
18 14-lead pinout for 20-terminal lead-less chip
    carrier
19 16-lead pinout for 20-terminal lead-less chip
    carrier
20 18-lead pinout for 20-terminal lead-less chip
    carrier
21 24-lead pinout for 28-terminal lead-less chip
    carrier
National annexes
NA (informative) Committees responsible
NB (informative) Cross-references

Details limiting conditions of use, recommended operating conditions, test methods and procedures and inspection requirements.