I.S. EN 61523-1:2002

SECTION
1 Overview
   1.1 Scope
   1.2 Purpose
   1.3 Contents of this standard
2 References
3 Definitions
4 Acronyms and abbreviations
5 Delay and power calculation system architecture
   5.1 Overview
   5.2 Procedural interface
        5.2.1 Global policies and conventions
        5.2.2 Flow of control
   5.3 DPCM - application relationships
        5.3.1 Technology library
        5.3.2 Subrule
   5.4 Inter-operability
6 Delay Calculation Language (DCL)
   6.1 Character set
   6.2 Lexical elements
        6.2.1 Whitespace
        6.2.2 Comments
        6.2.3 Tokens
        6.2.4 Header names
        6.2.5 Preprocessing directives
   6.3 Name spaces of identifiers
   6.4 Storage durations of objects
   6.5 Scope of identifiers
   6.6 Linkages of identifiers
        6.6.1 EXPORT
        6.6.2 IMPORT
        6.6.3 FORWARD
        6.6.4 Chaining of EXPOSE identifiers
   6.7 DCL data types
        6.7.1 Native data types
        6.7.2 Array types
        6.7.3 Derived data types
   6.8 Type conversions
        6.8.1 Implicit conversions
        6.8.2 Explicit conversions
   6.9 Operators
        6.9.1 String prefix operator
        6.9.2 Assignment operator
        6.9.3 New operator
        6.9.4 SCOPE operator
        6.9.5 Purity operator
        6.9.6 Timing propagation
        6.9.7 Timing checks
        6.9.8 Test mode operators
   6.10 Expressions
        6.10.1 Array subscripting
        6.10.2 Statement calls
        6.10.3 Assign variable reference
        6.10.4 Store variable reference
        6.10.5 Mathematical expressions
        6.10.6 Logical expressions and operators
        6.10.7 Pin range
        6.10.8 Embedded C code expressions
   6.11 Computation order
        6.11.1 Mathematical expressions
        6.11.2 Logical expressions
        6.11.3 Passed parameters
        6.11.4 WHEN clause
        6.11.5 REPEAT - UNTIL clause
   6.12 DCL statements
        6.12.1 Clauses
        6.12.2 Modifiers
        6.12.3 Prototypes
        6.12.4 Statement failure
        6.12.5 Interfacing statements
        6.12.6 Calculation statements
        6.12.7 METHOD statement
   6.13 Tables
        6.13.1 TABLEDEF statement
        6.13.2 Table visibility rules
        6.13.3 TABLE statement
        6.13.4 Static tables
        6.13.5 Dynamic tables
        6.13.6 Dynamic table manipulation
        6.13.7 Lookup table
   6.14 Library control statements
        6.14.1 Meta-variables
        6.14.2 SUBRULE statement
        6.14.3 SUBRULES statement
        6.14.4 TECH_FAMILY statement
   6.15 Modelling
        6.15.1 Model organization
        6.15.2 MODELPROC statement
        6.15.3 SUBMODEL statement
        6.15.4 Modeling statements
   6.16 Embedded C code
   6.17 Definition of a subrule
7 Power modelling and calculation
   7.1 Power overview
   7.2 Caching state information
        7.2.1 Initializing the state cache
        7.2.2 State cache lifetime
   7.3 Caching load and slew information
        7.3.1 Loading the load and slew cache
        7.3.2 Load and slew cache lifetime
   7.4 Simultaneous switching events
   7.5 Partial swing events
   7.6 Power calculation
   7.7 Accumulation of power consumption by the design
   7.8 Group pin list syntax and semantics
        7.8.1 Syntax
        7.8.2 Semantics
        7.8.3 Example
   7.9 Group condition list syntax and semantics
        7.9.1 Syntax
        7.9.2 Semantics
        7.9.3 Example
   7.10 Sensitivity list syntax and semantics
        7.10.1 Syntax
        7.10.2 Semantics
        7.10.3 Example
   7.11 Group condition language
        7.11.1 Syntax
        7.11.2 Semantics
        7.11.3 Condition expression operator precedence
        7.11.4 Condition expressions referencing pin
                states and transitions
        7.11.5 Semantics of nonexistent pins
8 Procedural Interface (PI)
   8.1 Overview
        8.1.1 DPCM
        8.1.2 Application
        8.1.3 libdcmlr
   8.2 Control and data flow
   8.3 Architectural requirements
   8.4 Data ownership technique
        8.4.1 Persistence of data passed across the Pl
        8.4.2 Data cache guidelines for the DPCM
   8.5 Application/DPCM interaction
        8.5.1 Application initializes message/memory
                handling
        8.5.2 Application loads and initializes the DPCM
        8.5.3 Application requests timing models for cell
                instances
        8.5.4 Model domain issues
        8.5.5 DPCM invokes application modeling callback
                functions
        8.5.6 Application requests propagation delay
        8.5.7 DPCM calls application EXTERNAL functions
   8.6 Re-entry requirements
   8.7 Application responsibilities when using a DPCM
        8.7.1 Standard structures rules
        8.7.2 User object registration
        8.7.3 Selection of early and late slew values
   8.8 Application use of the DPCM
        8.8.1 Initialization of DPCM
        8.8.2 Use of the DPCM
        8.8.3 Termination of the DPCM
   8.9 DPCM library organization
        8.9.1 Multiple technologies
        8.9.2 Model names
   8.10 DPCM error handling
   8.11 C level language foe EXPOSE and EXTERNAL functions
        8.11.1 Integer return code
        8.11.2 The Standard Structure pointer
        8.11.3 Result structure pointer
        8.11.4 Passed arguments
        8.11.5 DCL array indexing
        8.11.6 Conversion to C data types
        8.11.7 include files
   8.12 PIN and BLOCK data structure requirements
   8.13 DCM_STD_STRUCT Standard Structure
        8.13.1 Alternate semantics for Standard Structure
                fields
        8.13.2 Reserved fields
        8.13.3 Standard Structure value restriction
   8.14 DCMTransmittedInfo structure
   8.15 Environment or user variables
   8.16 PI functions summary
        8.16.1 Expose functions
        8.16.2 External functions
        8.16.3 Implicit functions
        8.16.4 Pl function table description
   8.17 PI function descriptions
        8.17.1 Interconnect loading related functions
        8.17.2 Interconnect delay related functions
        8.17.3 Functions assessing netlist information
        8.17.4 Functions exporting limit information
        8.17.5 Function getting/setting model information
        8.17.6 Functions importing instance name information
        8.17.7 Process information functions
        8.17.8 Miscellaneous standard interface functions
        8.17.9 Power related functions
        8.17.10 Array manipulation functions
        8.17.11 Initialization functions
        8.17.12 Calculation functions
        8.17.13 Modeling functions
   8.18 86Standard structure (dcmstd_stru.h) file
   8.19 Standard macros (dcmstd_macs.h) file
   8.20 Standard interface structures (dcmintf.h) file
   8.21 Standard loading (dcmload.h) file
   8.22 Standard debug (dcmdebug.h) file
   8.23 Standard array (dcmgarray.h) file
   8.24 DCM user array defines (dcmuarray.h) file
   8.25 Standard platform-dependency (dcmpltfm.h) file
   8.26 Standard state variables (dcmstate.h) file
   8.27 Standard table descriptor (dcmutab.h)
9 Parasitics
   9.1 Introduction
   9.2 Targeted applications for SPEF
   9.3 SPEF specification
        9.3.1 Grammar
        9.3.2 File syntax
        9.3.3 Escaping rules
        9.3.4 Comments
        9.3.5 File semantics
   9.4 Examples
        9.4.1 Basic D_NET file
        9.4.2 Basic R_NET file
        9.4.3 R_NET with poles and residues plus name
                mapping
        9.4.4 D_NET with triplet par_value
        9.4.5 R_NET with poles and residues plus triplet
                par_value
        9.4.6 Merging SPEF files
10 Physical design exchange
   10.1 Introduction
        10.1.1 Scope
        10.1.2 Targeted applications
   10.2 PDEF specification
        10.2.1 PDEF grammar
        10.2.2 PDEF file syntax
        10.2.3 Comments within a PDEF file
        10.2.4 PDF name semantics
        10.2.5 PDF file semantics
        10.2.6 Attributes
   10.3 Examples
        10.3.1 Escaping
        10.3.2 Clusters
        10.3.3 Global routing
        10.3.4 Symbolic placement constraints using PDEF
A Implementation requirements
B Calculation of total load capacitance in the DPCS
C Hold Control
D Bibliography
Figures
Tables

Enables circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, integrated circuit vendors to express timing and power information once (for a given technology), and EDA vendors to meet their application performance and capacity needs.