IEC 61943:1999

FOREWORD
1 General
    1.1 Scope and object
    1.2 Normative reference
2 Definitions
3 Principles for qualified manufacturer list
    (QML) approval
    3.1 Identification and definition of tasks
    3.2 Product specifications
4 Process design (task 1)
    4.1 Field of application
    4.2 Description of activities
    4.3 Interfaces and subcontracting procedures
    4.4 Procedures for design and verification of
          models
    4.5 Procedures for integration and validation
5 Integrated circuits design (task 2)
    5.1 Field of application
    5.2 Description of activities
    5.3 Interfaces
    5.4 Procedures for design and verification
    5.5 Validation procedure
6 Wafer fabrication (task 3)
    6.1 Field of application
    6.2 Description of activities
    6.3 Interfaces
    6.4 Validation procedure
7 Process characterization (task 4)
    7.1 Field of application
    7.2 Description of activities
    7.3 Interfaces
    7.4 Characterization process
8 Assembly and packaging (task 5)
    8.1 Field of application
    8.2 Description of activities
    8.3 Interfaces
    8.4 Validation procedures
9 Tests (task 6)
    9.1 Field of application
    9.2 Description of activities
    9.3 Interfaces - Validation of information provided
          by the customer or subcontractor
    9.4 Procedures
    9.5 Validation procedures

Defines how to apply the principles and requirements given in IEC 61739 to monolithic integrated circuits. The standard is applicable to those manufacturers of integrated circuits (ICs) who apply for manufacturing line approval.The objective is to establish consistency in the requirements used by manufacturers and auditors for techniques related to integrated circuit manufacturing.Each manufacturer may use his own methods for satisfying the requirements of this standard, provided that the required level of control in the manufacturing line is reached.