IEC 62530:2007
Superseded
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
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Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
07-11-2007
Publisher
Superseded date
31-12-2021
Superseded by
€488.44
Excluding VAT
Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>
| Committee |
TC 91
|
| DocumentType |
Standard
|
| Pages |
663
|
| PublisherName |
International Electrotechnical Committee
|
| Status |
Superseded
|
| SupersededBy |
| Standards | Relationship |
| BS IEC 62530:2007 | Identical |
| BS IEC 62530:2011 | Identical |
| BS EN 60950-23:2006 | Identical |
Summarise
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