IEC TR 63051:2017
Current
The latest, up-to-date edition.
Documentation on design automation subjects - Mathematical algorithm hardware description languages for system level modeling and verification (HDLMath)
Hardcopy , PDF , PDF 3 Users , PDF 5 Users , PDF 9 Users
English
10-01-2017
Important note : Users cannot be edited or removed once added to your Multi user PDF.
FOREWORD
INTRODUCTION
1 Scope
2 Normative references
3 Terms and definitions
4 Definition and positioning of HDLMath
5 Functional requirements of HDLMath
6 Comparison of current HDLMath languages
7 Conclusion
Bibliography
IEC TR 63051:2017(E) describes the main functional requirements for an HDLMath language and compares existing HDLMath languages from the viewpoint of designers. It is intended to accelerate the standardization of a mathematical algorithm design language and to help establish a new and good system modeling and verification environment.
| DevelopmentNote |
Stability Date: 2022. (01/2017)
|
| DocumentType |
Technical Report
|
| Pages |
16
|
| PublisherName |
International Electrotechnical Committee
|
| Status |
Current
|
| Standards | Relationship |
| PD IEC/TR 63051:2017 | Identical |
| IEC 61691-1-1:2011 | Behavioural languages - Part 1-1: VHDL Language Reference Manual |
| IEC 62530:2011 | SystemVerilog - Unified Hardware Design, Specification, and Verification Language |
| IEC TR 62856:2013 | Documentation on design automation subjects - The Bird's-eye View of Design Languages (BVDL) |
Access your standards online with a subscription
Features
-
Simple online access to standards, technical information and regulations.
-
Critical updates of standards and customisable alerts and notifications.
-
Multi-user online standards collection: secure, flexible and cost effective.