IEEE 1164-1993
Current
The latest, up-to-date edition.
IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)
English
26-05-1993
1 Overview
1.1 Scope
1.2 Conformance with this standard
2 Std_logic_1164 package declaration
3 Std_logic_1164 package declaration
Annex
A Using the Std_logic_1164 package
A.1 Value system
A.2 Handling strengths
A.3 Use of the uninitialized value
A.4 Behavioral modeling for 'U' propagation
A.5 'U's related to conditional expressions
A.6 Structural modeling with logical tables
A.7 X-handling: assignment of X's
A.8 Modeling with don't care's
A.9 Resolution function
A.10 Using Std_ulogic vs. Std_logic
This standard is embodied in the Std_logic_1164 package declaration and the semantics of the Std_logic_1164 package body along with this clause 1 documentation.
| Committee |
Design Automation
|
| DocumentType |
Standard
|
| ISBN |
978-0-7381-0991-6
|
| Pages |
24
|
| PublisherName |
Institute of Electrical & Electronics Engineers
|
| Status |
Current
|
| SupersededBy |
| BS IEC 61691-5:2004 | Behavioural langages VITALASIC (application specific integrated circuit) modeling specification |
| BS IEC 61691-1-1:2011 | Behavioural languages VHDL Language reference manual |
| EN 61691-3-3:2001 | Behavioural languages - Part 3-3: Synthesis in VHDL |
| I.S. EN 61691-1:1999 | DESIGN AUTOMATION - PART 1: VHDL LANGUAGE REFERENCE MANUAL |
| IEC 61691-5:2004 | Behavioural languages - Part 5: VITAL ASIC (application specific integrated circuit) modeling specification |
| IEEE DRAFT 1076.6 : D1.12A 99 | DRAFT STANDARD FOR VHDL REGISTER TRANSFER LEVEL SYNTHESIS |
| BS IEC 62050:2005 | VHDL register transfer level (RTL) synthesis |
| IEC 61691-6:2009 | Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions |
| BS EN 61691-1:1997 | Design automation VHDL language reference manual |
| IEC 62050:2005 | VHDL Register Transfer Level (RTL) synthesis |
| MIL-HDBK-62 Base Document:1996 | DOCUMENTATION OF DIGITAL ELECTRONIC SYSTEMS WITH VHDL |
| PD R217-020:2002 | Electronic system specification languages. VHDL modelling guidelines |
| IEEE 1076.4-2000 | IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification |
| IEC 61691-3-3:2001 | Behavioural languages - Part 3-3: Synthesis in VHDL |
| IEC 61691-1-1:2011 | Behavioural languages - Part 1-1: VHDL Language Reference Manual |
| IEEE DRAFT 1076.3 : 1995 | VHDL SYNTHESIS PACKAGES |
| IEEE 1076.6-2004 | IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis |
| IEEE 1076.3-1997 | IEEE Standard VHDL Synthesis Packages |
| EN 61691-1 : 1997 | DESIGN AUTOMATION - PART 1: VHDL LANGUAGE REFERENCE MANUAL |
| IEEE 1076.6-1999 | IEEE Standard for VHDL Register Transfer Level Synthesis |
Important note : Users cannot be edited or removed once added to your Multi user PDF.Access your standards online with a subscription
Features
-
Simple online access to standards, technical information and regulations.
-
Critical updates of standards and customisable alerts and notifications.
-
Multi-user online standards collection: secure, flexible and cost effective.