IEEE 1800.2-2017
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
View Superseded by
IEEE Standard for Universal Verification Methodology Language Reference Manual
14-09-2020
26-05-2017
1. Overview
2. Normative references
3. Definitions, acronyms, and abbreviations
4. UVM class reference
5. Base classes
6. Reporting classes
7. Recording classes
8. Factory classes
9. Phasing
10. Synchronization classes
11. Container classes
12. UVM TLM interfaces
13. Predefined component classes
14. Sequences classes
15. Sequencer classes
16. Policy classes
17. Register layer
18. Register model
19. Register layer interaction with RTL
design
Annex A (informative) - Bibliography
Annex B (normative) - Macros and defines
Annex C (normative) - Configuration and resource
classes
Annex D (normative) - Convenience classes, interface,
and methods
Annex E (normative) - Test sequences
Annex F (normative) - Package scope functionality
Annex G (normative) - Command line arguments
Defines the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments.
| Committee |
Design Automation
|
| DocumentType |
Standard
|
| PublisherName |
Institute of Electrical & Electronics Engineers
|
| Status |
Superseded
|
| SupersededBy |
| IEEE 1800-2012 | IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language |
| IEEE 1685-2014 | IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows |
| IEEE/Open Group 1003.1, 2013 Edition | IEEE Standard for Information Technology—Portable Operating System Interface (POSIX(TM)) Base Specifications, Issue 7 |
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