IEEE 1800.2-2020 REDLINE
Current
Current
The latest, up-to-date edition.
IEEE Standard for Universal Verification Methodology Language Reference Manual
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
14-09-2020
€290.70
Excluding VAT
This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments.
| Committee |
Design Automation
|
| DocumentType |
Standard
|
| ISBN |
978-1-5044-6806-0
|
| Pages |
752
|
| PublisherName |
Institute of Electrical & Electronics Engineers
|
| Status |
Current
|
| Supersedes |
| IEEE 1800-2017 | IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language |
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