IEEE DRAFT 1285 : D2.25 2005

1 Overview
  1.1 Document scope and purpose
  1.2 Scalable storage interface properties
  1.3 Historical perspective
  1.4 Non-storage applications
  1.5 S[2]I command execution
  1.6 S[2]I topologies
  1.7 S[2]I interconnects
  1.8 Memory mapped addresses
  1.9 Shared memory-mapped registers
2 References
3 Glossary and notation
  3.1 Definitions
  3.2 Field names
  3.3 C code notation
  3.4 Bit and byte ordering
  3.5 Generic delta-level command lists
  3.6 Data formats
4 Abbreviations and acronyms
5 Alpha-level interface
  5.1 Alpha-level overview
  5.2 Command execution
  5.3 Alpha4 command and status entries
  5.4 Alpha8 command and status entries
  5.5 Command processing
  5.6 Alpha-level CSRs
6 Delta interface properties
  6.1 Delta level distinctions
  6.2 Delta-level memory-mapped addresses
  6.3 Address formats
  6.4 Command lists
  6.5 Legacy command-set support
  6.6 Delta-level command processing
  6.7 Command sequence ordering
  6.8 Input/output
  6.9 Scatter/gather transfers
  6.10 System-bus transactions
  6.11 Status reports
  6.12 Command synchronization
  6.13 Error conditions
  6.14 Delta level mover CSRs
  6.15 Operational mover states
7 Delta interfaces
  7.1 Delta16 overview
  7.2 Delta32 overview
  7.3 Delta32 Mover CSRs
  7.4 Delta64 overview
Annexes
Annex A (informative) Bibliography
Annex B (informative) Illustrative applications
      B.1 Secure logins
      B.2 Scattered buffer allocation
      B.3 Heartbeat timers
      B.4 Event reports
      B.5 Power-level management
      B.6 Timed command execution
      B.7 DiskLite architecture
Annex C (informative) Software based RAID
      C.1 RAID I/O driver software
      C.2 Single-block OUTPUT
      C.3 Striped-block OUTPUT
      C.4 Erasure-correcting single-block INPUT
      C.5 Erasure-correcting multiple-block INPUT
Annex D (informative) Physical interface possibilities
      D.1 Delta16-level backplane interface
      D.2 Delta64 Serial Bus interface
Annex E (informative) C-code illustrations

Presents efficient physical-layer independent interface architecture for storage units that attach directly to memory access buses. In this interface model, storage units have an attachment to main memory, rather than an attachment to an I/O channel. This simplifies the storage unit design and supports scheduling of data transfers spanning large numbers of units.