ISO/IEC 18372:2004
Current
The latest, up-to-date edition.
Information technology — RapidIO(TM) interconnect specification
Hardcopy , PDF , PDF 3 Users , PDF 5 Users , PDF 9 Users
English
15-12-2004
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The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-toboard communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.
| Committee |
ISO/IEC JTC 1/SC 25
|
| DocumentType |
Standard
|
| Pages |
405
|
| PublisherName |
International Organization for Standardization
|
| Status |
Current
|
| Standards | Relationship |
| DS/ISO/IEC 18372:2004 | Identical |
| NEN ISO/IEC 18372 : 2005 | Identical |
| ISO/IEC 8802-3:2000 | Information technology Telecommunications and information exchange between systems Local and metropolitan area networks Specific requirements Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications |
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