JEDEC JESD 78E:2016
Superseded
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
View Superseded by
IC LATCH-UP TEST
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
23-11-2018
Publisher
Superseded date
25-02-2022
Superseded by
Free
Excluding VAT
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits.
| Committee |
JC-14.1
|
| DocumentType |
Revision
|
| Pages |
0
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Superseded
|
| SupersededBy | |
| Supersedes |
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| DSCC 15240 : 2019 | MICROCIRCUIT, DIGITAL, RADIATION HARDENED, HIGH SPEED CMOS, 16 BIT BUS SWITCH, MONOLITHIC SILICON<br> |
| DSCC 11237 C : 2019 | MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 512K X 32-BIT (16M) WITH EMBEDDED EDAC, LOW VOLTAGE SRAM, MONOLITHIC SILICON |
| DSCC 93144 D : 2020 | MICROCIRCUIT, MEMORY, DIGITAL, CMOS, UV ERASABLE PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON |
| MIL-STD-883-1 Base Document:2019 | Environmental Test Methods for Microcircuits Part 1: Test Methods 1000-1999 |
| DSCC 15212C:2025 | MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2M x 32-BIT (64M), RADIATION-HARDENED, PIPELINED, SYNCHRONOUS SRAM (SSRAM), MONOLITHIC SILICON |
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