JEDEC JESD 8-15:2002
Superseded
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
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STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18)
Published date
01-01-2002
Publisher
Superseded date
23-11-2018
Superseded by
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This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V.
| DocumentType |
Standard
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| PublisherName |
JEDEC Solid State Technology Association
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| Status |
Superseded
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| SupersededBy |
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