JEDEC JESD 8-15A : 2003
Current
Current
The latest, up-to-date edition.
STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18)
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
01-09-2003
Publisher
Important note : Users cannot be edited or removed once added to your Multi user PDF.This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V.
| DocumentType |
Revision
|
| Pages |
22
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Current
|
| Supersedes |
| JEDEC JESD82-17.01:2023 | Definition of the SSTUA32S868 and SSTUA32D868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM Applications |
| JEDEC JESD82-27.01:2023 | Definition of the SSTUB32869 Registered Applications Buffer with Parity for DDR2 RDIMM |
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