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JEDEC JESD 8-15A : 2003
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STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18)
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
01-09-2003
Publisher
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V.
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