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JEDEC JESD403-1B:2022

Superseded

Superseded

A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.

View Superseded by

JEDEC Module Sideband Bus(SidebandBus)

Available format(s)

Hardcopy , PDF

Superseded date

19-12-2023

Superseded by

JEDEC JESD403-1C:2023

Language(s)

English

Published date

01-08-2022

Free

This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages.

DocumentType
Standard
Pages
58
PublisherName
JEDEC Solid State Technology Association
Status
Superseded
SupersededBy
Supersedes

JEDEC JESD82-531A:2024 DDR5 Clock Driver Definition (DDR5CK01)

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