JEDEC JESD47J.01:2017
Current
Current
The latest, up-to-date edition.
Stress-Test-Driven Qualification of Integrated Circuits
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
01-09-2017
Publisher
Free
Excluding VAT
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
| DocumentType |
Revision
|
| Pages |
30
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Current
|
| Supersedes |
| JEDEC JESD 22-A111B:2018 | EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES |
| CEI EN IEC 63287-2:2023 | Semiconductor devices - Guidelines for reliability qualification plans Part 2: Concept of mission profile |
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