JEDEC JESD47K:2018
Superseded
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
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STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
01-08-2018
Publisher
Superseded date
23-12-2022
Superseded by
€113.13
Excluding VAT
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
| DocumentType |
Standard
|
| Pages |
34
|
| ProductNote |
This standard also refer to JP-001,JS-001,JS-002
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Superseded
|
| SupersededBy | |
| Supersedes |
Summarise
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