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JEDEC JESD78F.01:2022

Superseded

Superseded

A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.

View Superseded by

IC Latch-Up Test

Available format(s)

Hardcopy , PDF

Superseded date

01-12-2023

Superseded by

JEDEC JESD78F.02:2023

Language(s)

English

Published date

01-12-2022

Free

This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress.

DocumentType
Standard
Pages
94
PublisherName
JEDEC Solid State Technology Association
Status
Superseded
SupersededBy
Supersedes

DSCC 99586D:2016 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 32,000 GATES, MONOLITHIC SILICON

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