JEDEC JESD82-17.01:2023
Current
Current
The latest, up-to-date edition.
Definition of the SSTUA32S868 and SSTUA32D868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM Applications
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
01-01-2023
Publisher
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This standard defines standard specifications of DC interface parameters, switching parameters, and test
loading for definition of the SSTUA32S868 and SSTUA32D868 registered buffer with parity test for DDR2 RDIMM applications.
| DocumentType |
Standard
|
| Pages |
32
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Current
|
| Supersedes |
| JEDEC JEP 104C.01 :2003 | REFERENCE GUIDE TO LETTER SYMBOLS FOR SEMICONDUCTOR DEVICES |
| JEDEC JESD 8-7A : 2006 | 1.8 V ± 0.15 V (Normal Range) and 1.2 V - 1.95 V (Wide Range) Power Supply Voltage and Interface Standard<br>for Nonterminated Digital Integrated<br>Circuits |
| JEDEC JESD 8-15A : 2003 | STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18) |
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