JEDEC JESD82-29A.01:2022
Current
Current
The latest, up-to-date edition.
DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
01-09-2022
Publisher
Free
Excluding VAT
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications.
| DocumentType |
Standard
|
| Pages |
78
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Current
|
| Supersedes |
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