JEDEC JESD82-29A:2010
Superseded
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
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Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
01-12-2010
Publisher
Superseded date
01-02-2023
Superseded by
Free
Excluding VAT
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications.
| DocumentType |
Standard
|
| Pages |
80
|
| ProductNote |
This standard also refers to JEDEC JEP 95, JEDEC JEP 104, JEDEC JESD21-C, JEDEC JESD8-11A
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Superseded
|
| SupersededBy |
| JEDEC JESD82-30.01:2023 | LRDIMM DDR3 Memory Buffer (MB) |
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