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JEDEC JESD82-531A:2024

Current

Current

The latest, up-to-date edition.

DDR5 Clock Driver Definition (DDR5CK01)

Available format(s)

Hardcopy , PDF

Language(s)

English

Published date

01-01-2024

Free

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications.

DocumentType
Standard
Pages
114
PublisherName
JEDEC Solid State Technology Association
Status
Current
Supersedes

JEDEC JESD79-5B:2022 DDR5 SDRAM
JEDEC JESD403-1B:2022 JEDEC Module Sideband Bus(SidebandBus)
ANSI/ESDA/JEDEC JS-001:2017 ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing - Human Body Model (HBM) - Component Level<br>

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