MIL-M-38510-244 Revision B:1984
Current
The latest, up-to-date edition.
Microcircuits, Digital, NMOS, 65,536 BIT, Dynamic Random Access Memory (DRAM), Monolithic Silicon
30-07-1984
1. SCOPE
2. APPLICABLE DOCUMENTS
3. REQUIREMENTS
4. QUALITY ASSURANCE PROVISIONS
5. PACKAGING
6. NOTES
APPENDIX - FUNCTIONAL ALGORITHMS AND TIMING SETS
Specifies monolithic silicon, N-channel, dynamic, NMOS, 64K bit ram microcircuits.
| DevelopmentNote |
B NOTICE 1 - Notice of Inactivation for new design. B NOTICE 2 - Notice of Validation but remains Inactive for New Design. B NOTICE 3 - Notice of Validation but remains Inactive for New Design. (02/2006) B NOTICE 4 - Notice of Validation but remains Inactive for New Design. (11/2010) NEW CHILD NOT 5 2020 IS ADDED
|
| DocumentType |
Standard
|
| Pages |
50
|
| ProductNote |
NEW CHILD NOT 5 2020 IS ADDED
|
| PublisherName |
US Military Specs/Standards/Handbooks
|
| Status |
Current
|
This specification covers the detail requirements for monolithic silicon, N-channel, dynamic, NMOS, 65, 536/1-bit, random access memory microcircuits utilizing a 128 cycle refresh architecture and having pin number 1 as a no-connect.
| MIL-STD-883 Revision K:2016 | Microcircuits |
| MIL-M-38510 Revision J:1991 | Microcircuits, General Specification for |
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