MIL-M-38510-244 Revision B Notice 5 - Validation:2020
Current
The latest, up-to-date edition.
Microcircuits, Digital, NMOS, 65,536 BIT, Dynamic Random Access Memory (DRAM), Monolithic Silicon
English
20-08-2020
This specification covers the detail requirements for monolithic silicon, N-channel, dynamic, NMOS, 65, 536/1-bit, random access memory microcircuits utilizing a 128 cycle refresh architecture and having pin number 1 as a no-connect.
| DocumentType |
Notice
|
| Pages |
1
|
| PublisherName |
US Military Specs/Standards/Handbooks
|
| Status |
Current
|
This specification covers the detail requirements for monolithic silicon, N-channel, dynamic, NMOS, 65, 536/1-bit, random access memory microcircuits utilizing a 128 cycle refresh architecture and having pin number 1 as a no-connect.
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