MIL-M-38510-244 Revision B Notice 5 - Validation:2020
Current
Current
The latest, up-to-date edition.
Microcircuits, Digital, NMOS, 65,536 BIT, Dynamic Random Access Memory (DRAM), Monolithic Silicon
Amendment of
Available format(s)
PDF
Language(s)
English
Published date
20-08-2020
Publisher
Important note : Users cannot be edited or removed once added to your Multi user PDF.This specification covers the detail requirements for monolithic silicon, N-channel, dynamic, NMOS, 65, 536/1-bit, random access memory microcircuits utilizing a 128 cycle refresh architecture and having pin number 1 as a no-connect.
| Committee |
FSC 5962
|
| DocumentType |
Notice
|
| Pages |
0
|
| PublisherName |
US Military Specs/Standards/Handbooks
|
| Status |
Current
|
Access your standards online with a subscription
Features
-
Simple online access to standards, technical information and regulations.
-
Critical updates of standards and customisable alerts and notifications.
-
Multi-user online standards collection: secure, flexible and cost effective.