SEMI M15 : 1998
Current
The latest, up-to-date edition.
POLISHED WAFER DEFECT LIMITS TABLE FOR SEMI-INSULATING GALLIUM ARSENIDE WAFERS
12-01-2013
Defines the maximum number of defects, by type, that an acceptable polished Semi-Insulating Gallium Arsenide (GaAs) wafer may exhibit. Document established separately from SEMI M15, in accordance with the latest requirements for the material in advanced applications, covers polished semi-insulating GaAs wafers A defect limits table may also be applicable to conducting GaAs wafers, except for the specification of Light Point Defects (LPD) mentioned hereinafter. "Polished" shall refer to wafers which have a chemical/mechanical or specular chemical finish applied to one side of the wafer, with the backside being as cut and etched, ground and etched, lapped and etched, or polished. Definition of defects is covered in ASTM Practices F 523 and F 154.
| DevelopmentNote |
Not available for sale from ILI, customer to contact SEMI. (05/2001)
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| DocumentType |
Standard
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| PublisherName |
Semiconductor Equipment & Materials Institute
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| Status |
Current
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| SEMI M54 : 2004(R2011) | GUIDE FOR SEMI-INSULATING (SI) GAAS MATERIAL PARAMETERS |
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