SN EN 61030 : 1993

Committees responsible<br>National foreword<br>Specification<br>1. Scope and main features of the Domestic Digital<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Bus (D2B)<br>2. Normative references<br>3. Definitions and abbreviations<br>3.1 Definitions<br>3.2 Abbreviations<br>4. Modes<br>5. Main transmission features of D2B<br>5.1 Communication-related functions<br>5.2 Characteristics of transmitted signals<br>6. Frame structure<br>7. Frame exchange protocols<br>7.1 Frame sequences and acknowledgements<br>7.1.1 Write sequence<br>7.1.2 Read sequence<br>7.2 Description of the frame protocol<br>7.2.1 Start bit<br>7.2.2 Mode bits<br>7.2.3 Master address bits<br>7.2.4 Slave address bits<br>7.2.4.1 Slave address acknowledge<br>7.2.5 Control bits<br>7.2.5.1 Interpretation of the four control bits<br>7.2.5.2 Control acknowledge<br>7.2.6 Data field<br>7.2.6.1 Data bits<br>7.2.6.2 End of data bit<br>7.2.6.3 Data parity bit<br>7.2.6.4 Data acknowledge bit<br>7.2.7 Acknowledgement data<br>7.2.8 Activating the lock/unlock function<br>7.2.9 Medium access protocol<br>7.2.9.1 Physical characteristics<br>7.2.9.2 Carrier sense<br>7.2.9.3 Collision detection<br>8. Bit formats<br>8.1 General bit format<br>8.2 Detailed description of the bit formats<br>8.2.1 Introduction<br>8.2.2 Start bit (see figure 8)<br>8.2.3 Arbitration bits (see figure 9)<br>8.2.4 Master to Slave bits (see figure 10)<br>8.2.5 Slave to Master bits (see figure 11)<br>9. Address allocation<br>9.1 Address space definition<br>9.2 Allocation of AV/C address codes (Service code <br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;0001)<br>9.3 Sub-devices<br>10. Data interpretation<br>10.1 Slave status<br>10.2 Lock address<br>10.3 Property memory<br>10.4 Data<br>10.5 Commands<br>10.5.1 Principles of the command table<br>10.5.2 The service classification commands<br>10.5.3 Addressing of sub-devices<br>10.5.4 The "END" command<br>11. Gateway communication<br>11.1 Gateway communication in the Japanese home bus<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;system (HBS) format<br>11.2 Gateway communication in the format specified <br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;with the OPR<br>11.3 Gateway addresses<br>12. Command extension<br>13. Multiple frame message format<br>14. Electrical specification of a D2B system<br>14.1 Typical circuit configuration (see figure 21)<br>14.2 Logical and electrical state relationship<br>14.3 Driver specification<br>14.4 Receiver specification<br>14.5 Cable specification<br>Annex<br>A. (normative) The command table<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Function commands - group<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Video commands<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Audio commands<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Deck/player commands<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Tuner commands<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Text function commands<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Function commands - specific<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Camera video commands<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Timer commands<br>Tables<br>1. D2B mode parameters<br>2. Mode bit allocation<br>3. Control code allocation<br>4. Allocation of type codes AV/C device or sub-device<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;(Service code 0001)<br>5. Allocation of type codes for additional devices or<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sub-devices (Service code (0011)<br>6. Slave status bit allocation<br>7. Bit allocation for mid and least significant lock<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;address nibbles<br>8. Bit allocation for most significant lock address<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;nibble<br>9. Bit allocation for OPR associated with the OPC <br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;"Begin 2"<br>10. SA' and DA' definition<br>11. Bit allocation of the OPR association with the OPC<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;"Begin 1" <br>12. Address allocation of gateways<br>Figures<br>1. Configuration<br>2. Structure of D2B frame<br>3. Flow chart showing frame exchange protocol<br>4. Sequence of frame bits during a Master to Slave<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;transfer - Write action<br>5. Sequence of frame bits during a Slave to Master<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;transfer - Read action<br>6. Frame format<br>7. Example of a D2B digital filter<br>8. Start bit<br>9. Arbitration bit<br>10. Master to Slave bit<br>11. Slave to Master bit<br>12. D2B Address Space<br>13. Typical D2B address for an AV/C device<br>14. Example of configuration with devices and sub-devices<br>15. Principles of the command table<br>16. Frame format of sub-device address<br>17. Format of SSDA and DSDA<br>18. D2B as sub system in a configuration with a Home<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Electronic Bus<br>19. Format of SA' and DA'<br>20. Frame format<br>21. Reference circuit<br>22. Driver delay times<br>23. Receiver delay times