SN EN 61691-1 : 1997
Current
The latest, up-to-date edition.
DESIGN AUTOMATION - PART 1: VHDL LANGUAGE REFERENCE MANUAL
12-01-2013
FOREWORD
Section 0 General
0.1 Scope and object
0.2 Structure and terminology
0.2.1 Syntactic description
0.2.2 Semantic description
0.2.3 Front matter, examples notes,
references and annexes
0.2.4 Normative reference
Section 1 Design entities and configurations
1.1 Entity declarations
1.1.1 Entity header
1.1.1.1 Generics
1.1.1.2 Ports
1.1.2 Entity declarative part
1.1.3 Entity statement part
1.2 Architecture bodies
1.2.1 Architecture declarative part
1.2.2 Architecture statement part
1.3 Configuration declarations
1.3.1 Block configuration
1.3.2 Component configuration
Section 2 Subprograms and packages
2.1 Subprogram declarations
2.1.1 Formal parameters
2.1.1.1 Constant and variable
parameters
2.1.1.2 Signal parameters
2.1.1.3 File parameters
2.2 Subprogram bodies
2.3 Subprogram overloading
2.3.1 Operator overloading
2.3.2 Signatures
2.4 Resolution functions
2.5 Package declarations
2.6 Package bodies
2.7 Conformance rules
Section 3 Types
3.1 Scalar Types
3.1.1 Enumeration types
3.1.1.1 Predefined enumeration types
3.1.2 Integer types
3.1.2.1 Predefined integer types
3.1.3 Physical types
3.1.3.1 Predefined physical types
3.1.4 Floating point types
3.1.4.1 Predefined floating point
types
3.2 Access types
3.2.1 Array types
3.2.1.1 Index constraints and
discrete ranges
3.2.1.2 Predefined array types
3.2.2 Record types
3.3 Access types
3.3.1 Incomplete type declarations
3.3.2 Allocation and deallocation of objects
3.4 File types
3.4.1 File operations
Section 4 Declarations
4.1 Type declarations
4.2 Subtype declarations
4.3 Objects
4.3.1 Object declarations
4.3.1.1 Constant declarations
4.3.1.2 Signal declarations
4.3.1.3 Variable declarations
4.3.1.4 File declarations
4.3.2 Interface declarations
4.3.2.1 Interface lists
4.3.2.2 Association lists
4.3.3 Alias declarations
4.3.3.1 Object aliases
4.3.3.2 Nonobject aliases
4.4 Attribute declarations
4.5 Component declarations
4.6 Group template declarations
4.7 Group declarations
Section 5 Specifications
5.1 Attribute specification
5.2 Configuration specification
5.2.1 Binding indication
5.2.1.1 Entity aspect
5.2.1.2 Generic map and port map
aspects
5.2.2 Default binding indication
5.3 Disconnection specification
Section 6 Names
6.1 Names
6.2 Simple names
6.3 Selected names
6.4 Indexed names
6.5 Slice names
6.6 Attribute names
Section 7 Expressions
7.1 Expressions
7.2 Operators
7.2.1 Logical operators
7.2.2 Relational operators
7.2.3 Shift operators
7.2.4 Adding operators
7.2.5 Sign operators
7.2.6 Multiplying operators
7.2.7 Miscellaneous operators
7.3 Operands
7.3.1 Literals
7.3.2 Aggregates
7.3.2.1 Record aggregates
7.3.2.2 Array aggregates
7.3.3 Function calls
7.3.4 Qualified expressions
7.3.5 Type conversions
7.3.6 Allocators
7.4 Static expressions
7.4.1 Locally static primaries
7.4.2 Globally static primaries
7.5 Universal expressions
Section 8 Sequential statements
8.1 Wait statement
8.2 Assertion statement
8.3 Report statement
8.4 Signal assignment statement
8.4.1 Updating a projected output waveform
8.5 Variable assignment statement
8.5.1 Array variable assignments
8.6 Procedure call statement
8.7 If statement
8.8 Case statement
8.9 Loop statement
8.10 Next statement
8.11 Exit statement
8.12 Return statement
8.13 Null statement
Section 9 Concurrent statements
9.1 Block statement
9.2 Process statement
9.3 Concurrent procedure call statements
9.4 Concurrent assertion statements
9.5 Concurrent signal assignment statements
9.5.1 Conditional signal assignments
9.5.2 Selected signal assignments
9.6 Component instantiation statements
9.6.1 Instantiation of a component
9.6.2 Instantiation of a design entity
9.7 Generate statements
Section 10 Scope and visibility
10.1 Declarative region
10.2 Scope of declarations
10.3 Visibility
10.4 Use clauses
10.5 The context of overload resolution
Section 11 Design units and their analysis
11.1 Design units
11.2 Design libraries
11.3 Context clauses
11.4 Order of analysis
Section 12 Elaboration and execution
12.1 Elaboration of a design hierarchy
12.2 Elaboration of a block header
12.2.1 The generic clause
12.2.2 The generic map aspect
12.2.3 The port clause
12.2.4 The port map aspect
12.3 Elaboration of a declarative part
12.3.1 Elaboration of a declaration
12.3.1.1 Subprogram declarations and
bodies
12.3.1.2 Type declarations
12.3.1.3 Subtype declarations
12.3.1.4 Object declarations
12.3.1.5 Alias declarations
12.3.1.6 Attribute declarations
12.3.1.7 Component declarations
12.3.2 Elaboration of a specification
12.4 Elaboration of a statement part
12.5 Dynamic elaboration
12.6 Execution of a model
Section 13 Lexical elements
13.1 Character set
13.2 Lexical elements, separators and delimiters
13.3 Identifiers
13.4 Abstract literals
13.5 Character literals
13.6 String literals
13.7 Bit string literals
13.8 Comments
13.9 Reserved words
13.10Allowable replacements of characters
Section 14 Predefined language environment
14.1 Predefined attributes
14.2 Package STANDARD
14.3 Package TEXTIO
Annex A Syntax summary
Annex B Glossary
Annex C Potentially nonportable constructs
Annex D Changes from IEEE Std 1076-1987
Annex E Related standards
Index
Specifies accurately the VHDL language, mainly for implementors of tools which support the language, together with advanced users of the language.
DocumentType |
Standard
|
PublisherName |
Swiss Standards
|
Status |
Current
|
Standards | Relationship |
DIN EN 61691-1:1998-02 | Identical |
I.S. EN 61691-1:1999 | Identical |
EN 61691-1 : 1997 | Identical |
IEC 61691-1:1997 | Identical |
BS EN 61691-1:1997 | Identical |
Access your standards online with a subscription
Features
-
Simple online access to standards, technical information and regulations.
-
Critical updates of standards and customisable alerts and notifications.
-
Multi-user online standards collection: secure, flexible and cost effective.