BS 6475:1984

Foreword
Committees responsible
Specification
0. Introduction
1. Scope
2. Definitions
3. Designation of a particular Eurobus
4. Compliance
5. Protocols for Eurobus A
6. Electrical and timing requirements
Appendices
A. Eurobus 10/A logical implementation
B. Eurobus 18/A logical implementation
C. Eurobus 26/A logical implementation
D. Eurobus 34/A logical implementation
E. Connector allocation
F. Examples of application of protocol rules
G. Method of address allocation for mixed data widths
H. Example of Eurobus backplane construction
J. Mechanical option 1: forced air convection cooled
     double Eurocard for UK Ministry of Defence use
     with Eurobus 18/A
K. Extender panel
L. Examples of the application of Eurobus A timing
     requirements
M. Bus receiver a.c. noise rejection
N. Test circuit and waveform for determination of
     transient sink current
Tables
1. Eurobus A protocol lines
2. Coding of byte mode/address space selection lines
3. Address recognition protocol (N = 7)
4. Address modifier codes to be recognized by slave
     devices of different widths sharing the same bus
5. Identification of symbols
6. Termination network resistor ratings
7. Termination network diode characteristics
8. Power supply ranges at the bus transmitters and
     receivers
9. D.C. characteristics of the bus transmitter/
     receiver pair
10. D.C. characteristics of the bus receiver
11. D.C. characteristics of the bus transmitter
12. A.C. noise rejection of the bus receiver
13. A.C. requirements of the bus transmitter
14. Current drawn from a bus line in the quiescent
     state
15. Current output to a bus line in the active state
16. Properties of waveform
17. Eurobus A timing
18. Eurobus 10/A byte address code
19. Eurobus 18/A byte address code
20. Eurobus 26/A byte address code
21. Eurobus 34/A byte address code
22. Eurobus 10/A allocation of connector pins to
     signals
23. Eurobus 18/A allocation of connector pins to
     signals
24. Example of Eurobus 18/A signal allocations in an
     actual implementation
25. Eurobus 26/A allocation of connector pins to
     signals
26. Eurobus 34/A allocation of connector B pins to
     signals
27. Eurobus 34/A allocation of connector A pins to
     signals
28. Allocation of an idle bus
29. Reallocation of a bus being used for a basic cycle
30. Reallocation of a bus being used for a Hold or
     Retain cycle
31. Interrupt cycle
32. Read cycle
33. Write cycle
34. Vector cycle
35. Cycle time-out using cycle abort
36. Memory protect using cycle abort
37. Resolution of deadly embrace
38. Slave asks arbiter to remove allocation from master
39. Address recognition protocol (N=15)
40. Address recognition protocol (N=23)
41. Address recognition protocol (N=31)
42. Input/output connector A
43. Input/output connector B
44. Minimal delays complying with timing requirements
Figures
1. Eurobus with some typical devices
2. Bus terminators
3. End terminator/spur card
4. Test circuit
5. Signal edge characteristics
6. Allocation of an idle bus and allocation of a bus
     already in use for a basic Read, Write and Vector
     cycle
7. Reallocation of a bus being used for a Hold or
     Retain cycle
8. Interrupt cycle
9. Read cycle
10. Write cycle
11. Vector cycle
12. Cycle time-out using cycle abort
13. Memory protect using cycle abort
14. Multiple buses
15. Resolution of deadly embrace
16. Slave asks arbiter to remove allocation from master
17. Backplane cross section
18. MOD standard forced air convection cooled double
     Eurocard for Eurobus 18/A
19. Side 1 (component side)
20. Side 2 (non-component side)
21. Test pulses
22. Test circuit for determination of bus receiver a.c.
     noise rejection
23. Test circuit for determination of transient sink
     current
24. Test waveform for determination of transient sink
     current

Specifies one of a family of interfaces for use in modular data acquisition, processing, communication and control systems for military, industrial and other applications.

This British Standard specifies a processor system bus interface known as Eurobus A that is one of a family of interfaces for use in modular data acquisition, communication and control systems for military, industrial and other applications.

NOTE 1 More detailed information about the requirements specified in this standard, including the data width and addressing capability, devices connected to the bus, bus allocation, bus transfers, interbus transfers and electrical requirements, and background information are given in clause 0.

NOTE 2 In this standard, upper case letters are used for the first letter of names of bus cycles.

NOTE 3 The titles of the publications referred to in this standard are listed on the inside back cover.