BS 7241:1989

National foreword
Committees responsible
Chapter 0: Scope
Chapter 1: Introduction to the IEC 822 VSB bus standard
1.1 Standard objectives of the IEC 822 VSB parallel
       Subsystem Bus of the IEC 821 VMEbus (Subsystem
       henceforth referred to as VSB)
1.2 VSB system elements
1.2.1 Basic definitions
1.3 VSB standard diagrams
1.4 Standard terminology
1.5 Protocol specification
Chapter 2: VSB data transfer bus
2.1 Introduction
2.2 Data Transfer Bus lines
2.2.1 Addressing lines
2.2.2 Data lines AD00-AD31
2.2.3 Control lines
2.3 DTB modules - Basic description
2.3.1 MASTER
2.3.2 SLAVE
2.4 Capabilities of MASTERS and SLAVES
2.4.1 Addressing capabilities
2.4.2 Data transfer capabilities
2.4.3 Interrupt capability
2.5 Interaction between MASTERS and SLAVES
2.5.1 Interaction between MASTERS and SLAVES during
       address broadcast phase
2.5.2 Interaction between MASTERS and SLAVES during the
       data transfer
2.5.3 Interaction between MASTERS and SLAVES during
       cycle termination
2.5.4 Interaction between the IHV MASTER and SLAVES
       during the INTERRUPT-ACKNOWLEDGE cycles
2.6 Data transfer bus timing specifications
Chapter 3: VSB data transfer bus arbitration
3.1 Introduction
3.1.1 Types of arbitration
3.2 Arbitration Bus lines
3.2.1 BREQ*
3.2.2 BUSY*
3.2.3 BGIN*/BGOUT*
3.3 Arbitration modules - Basic description
3.3.1 ARBITER
3.3.2 REQUESTER
3.4 Capabilities of the REQUESTER
3.4.1 Serial Arbitration
3.4.2 Parallel Arbitration capability
3.4.3 Power-up sequence
3.5 Interaction between the MASTER, its associated
       REQUESTER and/or its associated ARBITER
3.5.1 Acquisition of the DTB
3.5.2 Release of the DTB
3.5.3 Race conditions between MASTER requests and
       ARBITER grants
3.6 Arbitration bus timing specifications
Chapter 4: Electrical characteristics of VSB boards
4.1 Introduction
4.1.1 Terminology
4.2 Power distribution
4.2.1 D.C. voltage characteristics
4.2.2 Connector electrical ratings
4.3 Bus driving and receiving requirements
4.3.1 General
4.3.2 Driving and loading RULES for three-state lines
       (AD00-AD31, DS*, PAS*, LOCK*, SIZE0-SIZE1,
       SPACE0-SPACE1, WR*)
4.3.3 Driving and loading RULES for open-collector
       lines (AC, ACK*, AD24-AD31, ASACK0*-ASACK1,
       BREQ*, BUSY*, CACHE*, ERR*, IRQ*, WAIT*)
4.3.4 Driving and loading RULES for BGIN* and BGOUT*
4.3.5 Receiving RULES for the geographical addressing
       lines (GA0-GA2)
4.3.6 Additional information
4.4 Signal lines interconnection - Summary
Chapter 5: VSB backplane specifications
5.1 Introduction
5.2 Backplane physical characteristics
5.3 Power distribution
5.4 Backplane electrical characteristics
5.4.1 Characteristic impedance
5.4.2 Termination networks
5.5 Signal line interconnection
5.5.1 General
5.5.2 BGIN*/BGOUT* daisy-chain
5.5.3 Geographical addressing
5.5.4 Additional information
5.6 VSB pin assignment
Figures
1-1 Functional modules and sub-buses defined by the
       VSB standard
1-2 Signal timing notation
2-1 Data Transfer Bus functional block diagram
2-2 Block diagram: MASTER
2-3 Block diagram: SLAVE
2-4 General flow of a VSB cycle
2-5 General flow of an ADDRESS-ONLY cycle
2-6 Organization of data
2-7 General flow of a SINGLE-TRANSFER cycle
2-8 General flow of a BLOCK-TRANSFER cycle
2-9 General flow of an INTERRUPT-ACKNOWLEDGE cycle
2-10 Flow of the address broadcast phase
2-11 Flow of a write data transfer
2-12 Flow of a read data transfer
2-13 Flow of the termination of the cycle
2-14 Flow of an INTERRUPT-ACKNOWLEDGE cycle
2-15 Active MASTER, active IHV MASTER and active PAR
       REQUESTER, LOCK*, WR*, SIZE0-SIZE1 and SPACE0-
       SPACE 1 timing, SINGLE-TRANSFER, BLOCK-TRANSFER,
       INTERRUPT-ACKNOWLEDGE and ARBITRATION cycles
2-16 Active MASTER and SLAVES, address broadcast
       timing, ADDRESS-ONLY, SINGLE-TRANSFER and BLOCK-
       TRANSFER cycles
2-17 Active MASTER and SLAVES, cycle termination
       ADDRESS-ONLY cycles
2-18 Active MASTER and SLAVES, write data transfer
       timing, SINGLE-TRANSFER and BLOCK-TRANSFER cycles
2-19 Active MASTER and SLAVES, read data transfer
       timing, SINGLE-TRANSFER, BLOCK-TRANSFER and
       INTERRUPT-ACKNOWLEDGE cycles
2-20 IHV MASTER and INTV SLAVES, selection phase
       INTERRUPT-ACKNOWLEDGE cycles
2-21 MASTER and SLAVES intercycle timing
2-22 DTB control transfer timing
2-23 Skew between ASACK0* and ASACK1*
2-24 Skew between ACK* and ERR*
3-1 Arbitration bus functional block diagram
3-2 Block diagram: ARBITER
3-3 Block diagram: SER REQUESTER
3-4 Block diagram: PAR REQUESTER
3-5 Serial Arbitration flow diagram: two REQUESTERS
3-6 General flow of an ARBITRATION cycle
3-7 Flow of an ARBITRATION cycle
3-8 Flow of the power-up sequence
3-9 Active PAR REQUESTER, contending PAR REQUESTER
       and idle SLAVE ARBITRATION cycle
3-10 Power-up timing
4-1 VSB signal levels
5-1 VSB backplane dimensions
5-2 Cross-section of a backplane microstrip signal
       line
5-3 Zo versus line width
5-4 Co versus line width
5-5 Standard bus termination
5-6 BGIN*/BGOUT* daisy-chain illustration
5-7 Geographical addressing lines resistor/capacitor
       circuit
A1 Flow of the selection phase
A2 Selection phase control; a high level block
       diagram
A3 An example for the selection logic
NUMEROUS TABLES

A sophisticated sub-system bus capable of very high performance (multiple functions) in 32 bit microprocessors.